Flexible ECC/parity bit architecture

Details Flexible ECC/parity bit architecture Flexible ECC/parity bit architecture

1996-02-20

1999-10-12

Elmore, Reba I.

Excavating

371 402, G11C 2900

Patent

active

059663898

ABSTRACT:
A semiconductor memory device is disclosed which includes an input terminal for receiving, and an output terminal for producing a data word, each having a predetermined number of bits. An internal memory array stores a plurality of error correcting encoded codewords each encoding more than one data word. An error correcting encoder is coupled between the input terminal and the memory array for generating an error correcting encoded codeword, encoding the received data word, and storing the codeword in the internal memory array. An error correcting decoder is coupled between the internal memory array and the output terminal to retrieve an error correction encoded codeword from the internal memory array, correct any detected errors, and produce one of the more than one data words encoded in the retrieved codeword at the output terminal.

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