Flexible deterministic state machine

Details Flexible deterministic state machine Flexible deterministic state machine

1994-07-12

1996-09-17

Heckler, Thomas M.

395494, G06F 1200

Patent

active

055577822

ABSTRACT:
A computer system has a memory and has a processor coupled to the memory, the processor having an access control arrangement for delaying completion of a memory access until the occurrence of a control signal. A deterministic circuit coupled to the-processor and the memory has a register arrangement containing control information loaded by the processor, the deterministic circuit having a signal generation arrangement for generating the control signal. The signal generating arrangement includes a selective delay arrangement which can selectively delay generation of the control signal during an access to the memory by a time interval having a duration which is a function of the control information in the register arrangement.

REFERENCES:
Intel Corporation, "Programmable State Tracker Logic Overview", Intel486 SX/Intel 487 SX CPU Module Manual, Rev. 2.0, May, 1991; pp. 2 and 7.
Intel Corporation, "82350DT EISA Chipset System Architecture Overview", Chipset Focus Group, May, 1991, Rev. 2.0, Title pages, Table of Contents and pp. 1-47.

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