Flexible/compressed array macro design

Details Flexible/compressed array macro design Flexible/compressed array macro design

1983-01-27

1986-01-21

Larkins, William D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307303, 307468, 357 239, 357 41, 357 45, H01L 2704, H01L 2978

Patent

active

045660220

ABSTRACT:
A transistor array arrangement for providing high-density semiconductor logic circuits in double polysilicon technology is described. Semiconductor, for example, FET, logic circuits have four independent but simultaneously accessible FET devices which are formed by intersecting sets of polysilicon gate lines. The four FET devices share a common first diffusion, for example a source, surrounded by four logically independent second diffusions, for example drains. A three-bit decode device is made which includes this array design.

REFERENCES:
patent: 3783349 (1974-01-01), Beasom
patent: 4212026 (1980-07-01), Balasubramanian et al.
patent: 4282446 (1981-08-01), McElroy
patent: 4287571 (1981-09-01), Chakravarti et al.
Faggin, F. et al., Solid-State Electronics, Pergamon Press, 1970, vol. 13, pp. 1125-1143.

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