Flexible buffering scheme for multi-rate SIMD processor

Details Flexible buffering scheme for multi-rate SIMD processor Flexible buffering scheme for multi-rate SIMD processor

2006-07-04

2006-07-04

Nguyen, Steven (Department: 2668)

Multiplex communications

Communication techniques for information carried in plural...

Adaptive

C712S014000, C712S022000

Reexamination Certificate

active

07072357

ABSTRACT:
A single instruction, multiple data (SIMD) architecture for controlling the processing of plurality of data streams in a digital subscriber line (DSL) system has a memory for storing the data from the channels, a processor operatively coupled with the memory for processing data from the data streams, and a controller for controlling the processor. Storing the data in the memory de-couples the operating rate of the processor and the operating rate of the data streams.

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