Flexible addressing memory controller wherein multiple memory mo

Details Flexible addressing memory controller wherein multiple memory mo Flexible addressing memory controller wherein multiple memory mo

1994-07-20

1996-12-17

Asta, Frank J.

Boots, shoes, and leggings

395440, 39549701, 39549703, 36492692, 36496425, 36496578, 36496579, 364DIG1, 364DIG2, G06F 1206, G06F 1300

Patent

active

055863000

ABSTRACT:
A controller capable of performing the flexible addressing of memory modules. In one embodiment, involving cache memory, a cache controller maintains, for each slot in cache memory, a read base address and a write base address for the slot and certain characteristics of the SIMM residing in the slot. The use of separate write and read addresses permits more than one cache memory SIMM to be written to with a single write address and permits cache memory to be non-contiguous and thus more robust with respect to SIMM failures. The maintenance of a table of SIMM characteristics permits volatile and non-volatile SIMMs to be used together in cache memory.

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