Flexible addressing for drams

Details Flexible addressing for drams Flexible addressing for drams

1992-08-31

1994-01-11

Fears, Terrell W.

Static information storage and retrieval

Addressing

Multiplexing

36518902, 365233, 36523005, G11C 1300

Patent

active

052788016

ABSTRACT:
A memory controller for controlling access to a memory includes a mapper for mapping a physical address to a row address and a column address that are suitable for addressing first and second memory devices having the same memory capacity but different addressing formats, a multiplexer for multiplexing the row address and the column address onto a set of address lines for addressing the memory and a circuit for generating control signals for controlling access to the memory. In a preferred embodiment, the first memory devices are 16 Mb DRAMs which require asymmetric addressing, and the second memory devices are 16 Mb DRAMs which require symmetric addressing. The memory controller of the invention generates a row address and a column address for addressing both types of memory devices without having knowledge of the types of memory devices that are present in the memory.

REFERENCES:
patent: 5204841 (1993-04-01), Chappell et al.

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