Flexible addressing and sequencing system for operand memory and

Details Flexible addressing and sequencing system for operand memory and Flexible addressing and sequencing system for operand memory and

1983-03-11

1985-06-04

Thomas, James D.

Boots, shoes, and leggings

G06F 924, G06F 928, G06F 936, G06F 926

Patent

active

045218587

ABSTRACT:
A microprocessor computer includes a control store ROM, which is flexibly addressed, using a sequence register and base register, both of which are loaded from the microprocessor data loop. The sequence register and microinstruction register, the latter providing a pipeline for output control store microinstructions, are selectively accessed by a multiplexer. The output of this multiplexer, along with the output of the base register, provide the inputs to an adder which may selectively address a microinstruction in the control store, as specified by the output of the multiplexer, or as specified by the sum of the addresses from the multiplexer and the base register. The flexible address, in addition to addressing the control store, provides an address to micro-operand storage in a high speed RAM. This allows local storage of data that must be processed by the microprocessor under microprogram control in high through-put real time applications. The use of the multiplexer and adder permits flexible addressing of both microinstruction words and micro-operands in the control store by permitting the address to be specified by (a) the microinstruction register; (b) the sequence register; (c) the sum of the base and sequence register; or (d) the sum of the base and microinstruction register. This flexibility of addressing permits loop strings to be implemented in the control store and allows two-dimensional data arrays to be addressed in the micro-operand RAM.

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