Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-09-18
2001-07-24
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S405000
Reexamination Certificate
active
06266687
ABSTRACT:
BACKGROUND
The present invention relates generally to radio communication systems, or more particularly, to the use of a modified fast convolution algorithm in channelizers and de-channelizers of a radio communication system.
In radio base station applications for cellular, Land Mobile Radio (LMR), satellite, wireless local area networks (WLANs) and other communication systems, many receiving and transmitting channels are handled simultaneously. In the future, mobile terminals, i.e. mobile telephones, will also include this capability. Such systems include digital channelization and de-channelization structures in their receivers and transmitters, respectively. Channelization and de-channelization can be defined as the filtering, decimation/interpolation and the frequency conversion of the signals transmitted and received.
The traditional receiver architecture is illustrated in FIG.
1
. In
FIG. 1
, a Radio Frequency (RF) signal is received by the antenna
105
and then downconverted to an intermediate frequency (IF) by a RF front end
110
. The RF front end
110
consists of components such as Low Noise Amplifiers (LNAs), filters and mixers. The desired channel is then extracted by the receiver channelizer
120
. The analog channelizer
120
also consists of LNAs, mixers and filters.
The desired channel is then processed at baseband by the RX baseband processing unit
130
to produce the received digital data stream. Today, baseband processing generally consists of analog-to-digital conversion, digital filtering, decimation, equalization, demodulation, channel decoding, de-interleaving, data decoding, timing extraction, etc.
The traditional transmitter architecture in
FIG. 1
is the dual of the receiver architecture. The transmitted data is first processed by the TX baseband processing unit
140
which consists of data coding, interleaving, channel coding, modulation, interpolation filtering, digital-to-analog conversion, etc. The baseband channel is then converted to an IF frequency via the transmit de-channelizer
150
. The transmit analog de-channelizer
150
consists of filters, mixers and low power amplifiers. The IF signal is then converted to RF and amplified by the RF front end
160
which consists of mixers, filters, and a high power amplifier. Finally, the signal is transmitted by the antenna
165
.
FIG. 1
illustrates the traditional architecture for a single channel receiver and transmitter of a mobile terminal (i.e., mobile phone). In the case of a base station, multiple channels are processed in a similar way. On the receiver side, the path will split at some point to form multiple paths for each channel being processed. On the transmitter side, the channels will be processed individually and then combined at some point to form a multichannel signal. The point of the split and combination varies, and therefore, a variety of base station receiver and transmitter architectures can be created. More importantly, though, the traditional analog and digital interface is currently somewhere between the channelizer and baseband processing blocks.
The analog channelizer/dechannelizer is complex to design and manufacture, and therefore costly. In order to provide a cheaper and more easily produced channelizer/dechannelizer, the future analog and digital interface will lie, instead, somewhere between the RF front end and channelizer blocks. Future radio receiver and transmitter structures of this type are called a variety of names, including multistandard radio, wideband digital tuners, wideband radio or software radio, and they all require a digital channelizer/de-channelizer.
Efficient digital channelizer/de-channelizer structures, which perform filtering, decimation/interpolation and frequency conversion, are very important in terms of power consumption and die area on a per channel basis. One of the main goals of these structures is to integrate as many channels into a single Integrated Circuit (IC) as possible.
There are several known ways to achieve digital channelization/de-channelization. The following examples will assume that a wideband signal is sampled by an ADC. The wideband signal is centered at an Intermediate Frequency (IF) and typically consists of many Frequency Division Multiplexed (FDM) channels. The most obvious way is illustrated in FIG.
2
. This receiver architecture mimics the functions of a traditional analog channelizer with In-phase and Quadrature (IQ) frequency conversion using e.g. sin/cos generators, decimating and filtering on a per-channel basis. The bulk of the decimation filtering can be done with computationally cheap CIC filters. Integrated circuits containing this architecture are readily available from several manufacturers. One skilled in the art will appreciate that the dual of this architecture is also possible for the transmitter.
The IQ channelizer is flexible in that it can handle many standards simultaneously and the channels can be arbitrarily placed. Its main drawback is the need for IQ frequency conversion at a high input sampling frequency and subsequent decimation filters for each channel. This means that the die area and power consumption is relatively high per channel.
Another channelizer possibility is to build a decimated filter bank in the receiver, as shown in FIG.
3
. This method shares a common polyphase filter between many, or all, channels. The hardware cost for this structure is small since it is split between many channels, and good filtering can be achieved. Filter banks are also good for use in transmitter de-channelizers since they both interpolate and add the channels together. An example of this is illustrated in WO 9528045 “Wideband FFT Channelizer”.
Although these filter banks can be reconfigured to fit different standards, it is still difficult to accommodate multiple channel spacings at the same time. The decimated filter bank has a very low cost per channel, but only if all or the majority of channels are used. This architecture is also very inflexible since the channels have to lie on a fixed frequency grid with only one channel spacing being possible. Multiple standards make the filter bank concept require multiple sampling rates. This means that multiple architectures, including an analog-to-digital converter (ADC) and channelizer, are required for the simultaneous multiple standards.
A variation on the structure of the decimated filter bank, called a subsampled filter bank, can lower the computational cost at the expense of flexibility. For example, requirements for adaptive channel allocation, irregular channel arrangements and frequency hopping precludes using subsampled filter banks, since all channels must be available at the same time.
The third main channelization technique is based on the fast convolution scheme of the overlap-add (OLA) or overlap-save (OLS). Fast convolution is a means of using cyclic convolution to exactly perform linear convolution, i.e., Finite Impulse Response (FIR) filtering. The advantage of this technique is a lower computational requirement as compared to implementing the traditional form of linear convolution. Furthermore, it is possible to modify the basic fast convolution algorithm such that it is possible to simultaneously decimate/interpolate and frequency convert; however, as a result, the linear convolution is then only approximately performed. The modifications also reduce the computational complexity. The stand-alone modified fast convolution algorithm, as illustrated in “A Flexible On-board Demultiplexer/Demodulator”, Proceedings of the 12th AIAA International Communication Satellite Systems Conference, 1988, pp. 299-303, is claimed to be a very computationally efficient technique for systems containing a mixture of carrier bandwidths, and has been discussed for use in satellite systems.
The stand-alone modified fast convolution algorithm in the prior art performs all the filtering alone, without any additional signal processing. This method leads to various delays. However, delays are an inherent part of satellite systems, due to the transmission time
Hellberg Richard
Leyonhjelm Scott
Burns, Doane, Sweeker & Mathis, L.L.P.
Mai Tan V.
Telefonaktiebolaget LM Ericsson (publ)
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