Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
2000-01-11
2001-07-31
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S270000, C326S027000, C326S087000
Reexamination Certificate
active
06268750
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to digital output drivers for CMOS integrated circuits, and more particularly to a method and apparatus for flattening the output resistance response of digital output drivers.
BACKGROUND OF THE INVENTION
Integrated circuits are commonly packaged as chips. An integrated circuit within a chip communicates with the world outside the chip through metalization layers on the outside of the chip known as signal pads. In order for an integrated circuit within the chip to send signals outside of the chip, the integrated circuit requires an output driver circuit, which drives a signal from the integrated circuit onto an output signal pad.
The signal pads on a chip are connected to the packaging of the chip (e.g., a pin) which is then connected to a signal trace on a printed circuit board which runs to another integrated circuit chip or electronic device. The electrical connection of the signal pad through the packaging of the chip to the signal trace contains parasitic resistance, inductance, and capacitance which affects the transmission of the signal from the signal pad. This parasitic resistance, capacitance, and inductance is often referred to as the characteristic package impedance.
The signal trace itself also contains transmission line characteristics which include resistance, capacitance, and inductance, defined by the characteristic impedance of the printed circuit (PC) board transmission line, or Z
o
, which also affects the quality of the transmitted signal from the signal pad.
As known by those skilled in the art, it is important to match the driver output resistance R
o
of the output pad to the characteristic board impedance of the transmission line in order to avoid signal reflections due to voltage level switching on the pad, and therefore undesirable signal degradation.
Impedance matching of an output driver to the characteristic impedance of the signal trace presents several problems. First, process variations inherent in the manufacturing process of integrated circuits, such as the transistor implanting doping level, the effective length of channels in the field effect transistors (FETs), the thickness of the gate oxide for transistors, and the diffusion resistance, can cause the output resistance of two supposedly identical circuits to differ. In addition, variations in voltage and temperature can cause variations in the output resistance of a given chip. Specifically, the output resistance R
o
response can vary significantly as the signal on the pad transitions from one voltage level to another. In another example, when the temperature of an integrated circuit approaches its maximum operating temperature, the resistance of the FETs in the integrated circuit increases.
In view of the above, it is clear that a need exists for an output driver circuit that is characterized by a relatively constant output impedance R
o
over all process, voltage, and temperature ranges.
One prior art technique for accomplishing impedance matching of output pads for integrated circuits is described in U.S. pat. application Ser. No. [UNKNOWN], entitled “Digitally Controlled Output Driver and Method for Impedance Matching”, herein incorporated by reference for all that it teaches. Output driver impedance matching according to this technique is accomplished by programmably enabling various combinations of pull-up PFETs while driving the output pad high and various combinations of pull-down NFETS while driving the output pad low. While this type of programmed impedance matching significantly improves the output resistance curve, problems still remain. Due to the variations in the gate-to-source voltage Vgs, drain-to-source voltage Vds, and back gate voltage in the output driver's PFET and NFETs, the output resistance R
o
still varies as the output voltage Vo transitions between logic states. For example, a voltage transition from a logic level low state (“0”) to a logic level high state (“1”) can result in an output resistance variation of between 68% above and 36% below the target R
o
as measured at 10% V
o
and 90% V
o
. During a voltage transition from a logic level high state (“1”) to a logic level low state (“0”), the output resistance R
o
can vary between 57% above and 25% below the target R
o
as measured at 10% V
o
and 90% V
o
.
Accordingly, a need exists for a method and circuit for further improving the impedance matching of an output driver which results in an improved output resistance curve over all process, temperature, and voltage variations on an output pad.
SUMMARY OF THE INVENTION
The present invention is a novel method and apparatus for improving the output resistance response of a digital output driver that results from state level transitions in the output voltage. The invention delivers a precise, relatively constant driver output resistance R
o
during voltage level transitions on the output pad over all process, voltage, and temperature ranges.
In accordance with the invention, impedance matching is accomplished in an output driver by programmably enabling various combinations of pull-up PFETs when driving the output pad high and by programmably enabling various combinations of pull-down NFETs when driving the output pad low. A pull-up calibration word PU_N[n:
0
] is used to drive a pull-up PFET calibration array, while a pull-down calibration word PD[n:
0
] is used to drive a pull-down NFET calibration array. The calibration array FETs (PFETs and NFETs) are sized such that the FETs have conductances corresponding to their binary weighted bit position in their respective calibration word PU_N[n:
0
] or PD[n:
0
]. In other words, each FET in its respective pull-up PFET calibration array or pull-down NFET calibration array has a conductance of 2
(bit position)
G. Thus, if bit
0
of the calibration word controls a FET with conductance G, bit
1
of the calibration word controls a FET with a conductance 2*G, bit
2
of the calibration word controls a FET with a conductance 2*G, and so on. In effect, as the calibration word binary count increments, more resistors are added in parallel in the driver FET array, and the output resistance R
o
drops. Having separate and independent calibration word for each of the pull-up PFET calibration array and the pull-down NFET calibration array enables the output driver to offer precision impedance matching over all process, voltage, and temperature ranges.
In the present invention, an additional NFET is added to the pull-up PFET calibration array and an additional PFET is added to the pull-down NFET calibration array. The addition of these two FETs allows the output driver to supply more current during the initial stages of a voltage transition, resulting in a flatter overall output resistance R
o
response. For example, during a low-to-high transition, the pull-up NFET is conducting. As the output voltage V
o
approaches V
DD
−V
t
from 0V, the NFET enters the cut-off region and allows the calibrated pull-up PFET array to determine the driver's output resistance R
o
when (V
DD
−V
t
)≦V
o
≦V
DD
. The pull-down PFET behaves in a similar fashion during a high-to-low transition.
REFERENCES:
patent: 5773999 (1998-06-01), Park et al.
patent: 5887150 (1999-03-01), Schneider et al.
patent: 6133757 (2000-10-01), Huang et al.
Agilent Technologie,s Inc.
Lam Tuan T.
Nguyen Hiep
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