Electric lamp and discharge devices – With luminescent solid or liquid material – Solid-state type
Reexamination Certificate
2002-03-12
2004-12-21
Patel, Vip (Department: 2879)
Electric lamp and discharge devices
With luminescent solid or liquid material
Solid-state type
C313S506000, C313S509000
Reexamination Certificate
active
06833666
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of Korean Application No. 2001-47334 filed Aug. 6, 2001, in the Korean Patent Office, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flat panel display device and a method of manufacturing the same.
2. Description of Related Art
A flat panel display device includes a liquid crystal display (LCD), an organic electroluminescent (EL) display, a plasma display panel (PDP), and the like. Of these, the LCD and the organic EL display include a plurality of pixels having a transistor and a capacitor.
A method of increasing a capacitance of the capacitor includes increasing a surface area size of the capacitor, reducing a thickness of a dielectric layer of the capacitor, and using a material having a high dielectric constant as the dielectric layer.
Of these methods of increasing the capacitance of the capacitor, the method of increasing the surface area size of the capacitor reduces an aperture ratio due to an increased capacitor area, and the method of reducing the thickness of the dielectric layer of the capacitor requires an additional process.
Hereinafter, the flat panel display device is described focusing on the organic EL display device.
FIG. 1
is a cross-sectional view illustrating a conventional active matrix organic EL display device. A buffer layer
140
is formed on a transparent insulating substrate
100
. The transparent insulating substrate
100
includes first, second and third regions
110
,
120
and
130
, respectively, and is preferably made of glass. The buffer layer
140
is preferably made of an oxide layer.
A semiconductor layer
111
is formed on the buffer layer
140
over the first region
110
. A gate insulting layer
150
is formed over the whole surface of the substrate
100
and covers the semiconductor layer
111
.
A first metal layer is deposited on the gate insulating layer
150
and patterned to form a gate electrode
112
and a first capacitor electrode
122
. The gate electrode
112
is formed over the first region
110
, and the first capacitor electrode
122
is formed over the second region
120
.
A p-type impurity or an n-type impurity is ion-doped into the semiconductor layer
111
using the gate electrode
112
as a mask to form source and drain regions
113
and
114
.
An interlayer insulating layer
160
is formed over the whole surface of the substrate
100
including the semiconductor layer
111
and the gate electrode
112
. The gate insulating layer
150
and the interlayer insulating layer
160
are etched to form contact holes
161
and
162
. The contact holes
161
and
162
expose portions of the source and drain regions
113
and
114
, respectively.
A second metal layer is deposited on the interlayer insulating layer
160
, filling the contact holes
161
and
162
. The second metal layer is patterned to form source and drain electrodes
115
and
116
and a second capacitor electrode
126
. The source and drain electrodes
115
and
116
contact the source and drain regions
113
and
114
through the contact holes
161
and
162
, respectively. The second capacitor electrode
126
extends from the source electrode
115
to cover the first capacitor electrode
122
.
A passivation layer
170
is formed over the whole surface of the substrate
100
. The passivation layer
170
is etched to expose either of a portion of the source electrode
115
and a portion of the drain electrode
116
so as to form a via hole
171
. In
FIG. 1
, the via hole
171
exposes a portion of the drain electrode
116
.
A transparent conductive material layer is deposited on the passivation layer
170
, filling the via hole
171
. The transparent conductive material layer is patterned to form a pixel electrode
131
over the third region
130
of the substrate
100
. The pixel electrode
131
contacts the drain electrode
116
through the via hole
171
, and is made of indium tin oxide (ITO) or indium zinc oxide (IZO).
A planarization layer
180
is formed over the whole surface of the substrate
100
. The planarization layer
180
is etched to expose a portion of the pixel electrode
131
so as to form an opening portion
181
.
An organic EL layer
132
is formed on the pixel electrode
131
to cover the opening portion
181
. A cathode electrode
133
is formed to cover the organic EL layer
132
. Accordingly, the organic EL display of
FIG. 1
is completed.
The interlayer insulating layer
160
serves as both an insulating layer to insulate the gate electrode
112
from the second metal layer and a dielectric layer of the capacitor. Preferably, a portion of the interlayer insulating layer
160
over the first region
110
is relatively thick so as to obtain an excellent insulating characteristic, whereas a portion of the interlayer insulating layer
160
over the second region
120
is relatively thin so as to increase the capacitance of the capacitor. However, forming the relatively thick portion of the interlayer insulating layer
160
and the relatively thin portion of the interlayer insulating layer
160
requires an additional process. Also, an increase of a surface area of the capacitor for a high capacitance causes a reduction of an aperture ratio.
SUMMARY OF THE INVENTION
To overcome the problems described above, the present invention provides a flat panel display device having both a high capacitance of a capacitor and a sufficient insulating characteristic of a thin film transistor (TFT) without requiring an additional process.
It is an object of the present invention to provide a flat panel display device having both a high capacitance of a capacitor and a high aperture ratio.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and, in part, will be obvious from the description, or may be learned by practice of the invention.
In order to achieve the above and other objects of the invention, the present invention provides a flat panel display device, comprising: an insulating substrate including a thin film transistor region and a capacitor region, the thin film transistor region comprising a thin film transistor having a semiconductor layer, a gate electrode and source and drain electrodes, the capacitor region comprising a capacitor having first and second capacitor electrodes; and an insulating layer formed on the insulating substrate, a portion of the insulating layer formed over the thin film transistor region insulating the gate electrode from the source and drain electrodes, and a portion of the insulating layer formed over the capacitor region used as a dielectric layer between the first capacitor electrode and the second capacitor electrode, the portion of the insulating layer formed over the thin film transistor region is thicker in thickness than the portion of the insulating layer formed over the capacitor region.
The present invention further provides a flat panel display device, comprising: an insulating substrate including a thin film transistor region and a capacitor region; a semiconductor layer formed on the thin film transistor region of the insulating substrate; an insulating layer formed over the whole surface of the insulating substrate and covering the semiconductor layer; a gate electrode formed on the gate insulating layer over the thin film transistor region of the insulating substrate; a first capacitor electrode formed on the gate insulating layer over the capacitor region of the insulating substrate; an interlayer insulating layer formed over the whole surface of the insulating substrate and covering the gate electrode and the first capacitor electrode, a portion of the insulating layer formed over the thin film transistor region is thicker in thickness than a portion of the insulating layer formed over the capacitor region, the insulating layer having contact holes exposing both end portions of the semiconductor layer; source and drain electrodes formed on the interlayer insu
Koo Jae-Bon
Seo Seong-Moh
Patel Vip
Samsung SDI & Co., Ltd.
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