Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-01-27
2001-05-08
Chow, Dennis-Doon (Department: 2775)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S096000
Reexamination Certificate
active
06229512
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix type flat panel display unit and a display method thereof and more particularly to a flat panel display unit and a display method thereof whose driving method in non-displaying the predetermined video signal lines is improved.
2. Description of the Related Art
With the progress of the late highly advanced information society, the role of a display unit for displaying such information is increasing and a high definition, multi-gradation, down-sized, low power consumption and low cost display unit is now strongly desired. Under such circumstances, a variety of display units have been proposed and put into practical use. Among them, an active matrix type liquid crystal display is drawing attention as a display unit fulfilling such requirements.
One disclosed in JP-A-3-292088 may be cited as a conventional example using such active matrix type flat panel display unit as a display unit for displaying TV video signals. According to the technology described in JP-A-3-292088, a predetermined number of scanning line signals of a video signal are not used for displaying the image in accordance with a PAL system video signal having scanning signal lines whose number is larger than that of the display scan lines of the flat panel display unit for the NTSC system.
The structure of the active matrix type liquid crystal display panel will be explained below at first. As is well known, a plurality of signal lines, scan lines, TFTs (thin film transistors) as switching elements and pixel electrodes are arrayed in a matrix form on a surface of a first glass substrate, and color filters of red (R), green (G) and blue (B) for example for realizing color display, a counter electrode and others are formed on a surface of a second glass substrate in the liquid crystal display panel. It is then constructed by filling liquid crystal substance between the both glass substrates.
A signal line driving section (so-called a source driver) for controlling the signal lines of the liquid crystal display panel is a circuit for outputting pixel signal voltages corresponding to the respective signal lines and comprises a sampling pulse generating circuit, level shifters, sample and hold circuits using analog switches and sampling capacitors, an output circuit using an operational amplifier and a hold capacitor and others.
FIG. 7
is a timing chart showing a conventional driving method. Two sample and hold circuits (A and B) per each signal line outputs one of positive (+) and negative (−) polar pixel signal voltages (a, b, . . . ) to the signal line while sampling and holding them alternately from a video signal by switching the circuits A and B alternately per one horizontal scan period. It is noted that an inhibit signal INH in
FIG. 7
is a control signal of the sample and hold circuit in the signal line driving section for controlling the switching of the two circuits (A and B) of the sample and hold circuit. A control signal OE is a signal for controlling such drive.
At first, the video signal inputted to the signal line driving section is sampled sequentially by a sampling clock corresponding to each signal line during each horizontal scan period. The start of the sampling within each horizontal scan period is controlled by a start pulse signal. The sampled signal (pixel signal voltage, abbreviated as “P.S.V.” in the figure) is stored in the sample and hold circuit. At this time, one of two sample and hold circuits is selected. During the next horizontal scan period, the sample and hold circuit is switched to the other one (e.g., from A to B or B to A) by the inhibit signal INH. In the same time, the pixel signal voltage sampled during the previous horizontal scan period is outputted to the corresponding signal line.
For instance, pixel signal voltage (a) having + polarity is sampled and is stored in the A circuit of the sample and hold circuit during the first horizontal scan period. In the next horizontal scan period, the circuits (A and B) for sampling and holding a pixel signal voltage and the circuits (A and B) for outputting a pixel signal voltage which is stored therein are switched in accordance with the inhibit signal INH, the + polar pixel signal voltage a stored in the A circuit is outputted to the signal line and in the same time, pixel signal voltage (b) having − polarity is sampled and stored in the B circuit (see line 1).
In the next horizontal scan period, the circuits (A and B) are switched in accordance with the inhibit signal INH, the − polar pixel signal voltage (b) stored in the B circuit is outputted to the signal line and in the same time, pixel signal voltage (c) having + polarity is sampled and stored in the A circuit (see line 2). Similarly to that, in the next horizontal scan period, the circuits (A and B) are switched in accordance with the inhibit signal INH, the pixel signal voltage (c) having the + polarity and stored in the A circuit is outputted to the signal line and in the same time, pixel signal voltage (d) having + polarity is sampled and stored in the B circuit (see line 3). While a pixel signal voltage corresponding to the display scan line between the display scan lines 3 and 4 is not used for displaying in
FIG. 7
, the above-mentioned control is repeated sequentially when every pixel signal voltage should be used for displaying.
When the pixel signal voltage is outputted from the above-mentioned sample and hold circuit to the signal line so as to apply the voltage to the pixel electrode, a gate of a TFT connected to the pixel electrode must be turned on. It is implemented by a gate pulse outputted from a gate line driving section called a gate driver. The gate driver outputs the gate pulse sequentially to a corresponding scan line with inputted clock pulse. For instance, the TFT turns on at the leading edge of the gate pulse and turns off at the trailing edge thereof.
Next, the present situation of the drive technique in selective non-displaying of image signal will be explained. When a video signal of the PAL system is inputted to a display unit having a number of scanning line signals corresponding to the NTSC system, its image may be displayed in the PAL system across the whole screen by deleting pixel signal voltage corresponding to the predetermined display scan lines by the control signal OE during one horizontal scan period among six horizontal scan periods.
As for the pixel signal voltage and the counter electrode signal, the polarity of the pixel signal voltage not used in displaying images is kept same with that of the pixel signal voltage in the previous horizontal scan period so that the polarity is inverted per horizontal scan period contributing to the display. In the same time, the polarity of the counter electrode signal is not inverted within the horizontal scan period during which the pixel signal voltage is not used in displaying images.
That is, because the polarity of the video signal is not inverted and is kept same during the horizontal scan period prior to the horizontal scan period of the pixel signal voltage which is not used in displaying images, the + polar pixel signal voltage (d) is sampled and stored in the B circuit in the same time when the + polar pixel signal voltage (c) is outputted from the A circuit of the sample and hold circuit to the signal line for example. Then, the circuits (A and B) are switched and pixel signal voltage (e) having − polarity is sampled and stored in the A circuit during the next horizontal scan period during which the pixel signal voltage is not used for displaying. During the next horizontal scan period, the circuits (A and B) are switched and the pixel signal voltage (e) having the − polarity stored in the A circuit is outputted to the signal line and pixel signal voltage (f) having the + polarity is sampled and stored in the same time.
The problem of the conventional driving method described above lies in that the case when t
Chow Dennis-Doon
Kabushiki Kaisha Toshiba
Pillsbury Madison & Sutro LLP
LandOfFree
Flat panel display unit and display method of the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flat panel display unit and display method of the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flat panel display unit and display method of the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2446581