Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1999-09-23
2002-07-09
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S206000
Reexamination Certificate
active
06417847
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for driving signal lines of a flat-panel display, such as a liquid crystal display device, in which plural signal lines and scanning lines are arranged in a matrix form.
2. Related Background Art
Flat-panel display devices, such as active-matrix liquid crystal display devices employing thin film transistors (TFTs) are widely used as displays for computers etc., because of their high response speed and high resolution. As portable apparatus such as notebook-size computers become prevalent, driver integrated type of liquid crystal display devices, in which a liquid crystal display part and a driving circuit part are formed on a common substrate in the same process, attract someone's notice.
FIG. 1
is a block diagram schematically showing a structure of a signal line driving circuit of an driver integrated type of liquid crystal display device, which has a shift register
51
for sequentially shifting start pulses XST inputted from outside, buffers
41
-
4
n
each connected to corresponding output terminals of the shift register
51
, and analog switches
5
, ons and offs of which are controlled by output signals from the buffers
41
-
4
n.
The signal line driving circuit of
FIG. 1
carries out a so-called block sequence driving, in which a plurality of signal lines are simultaneously driven as a block. By such a block sequence driving, it is possible to lower the frequencies of shift clock signals XCK and /XCK of the shift register
51
, thereby increasing the number of signal lines S
1
, S
2
, . . . , Sn. Accordingly, it is possible to improve display resolution.
FIG. 2
is a timing chart of input and output signals of the signal line driving circuit shown in FIG.
1
. In FIG.
2
, a V-line inversion driving is carried out.
The operations of the signal line driving circuit of
FIG. 1
will be explained below with reference to FIG.
2
. The shift clock signals XCK and /XCK are inputted to the shift register
51
. The logic of XCK is inverted relative to that of /XCK. In
FIG. 2
, a start pulse XST is inputted at the time T
11
. The shift register
51
then starts the shift operation and each output terminal of the shift register
51
outputs the shift pulse in order.
A shift pulse is then outputted from an output terminal of the shift register
51
at the time T
12
, thereby turning ON an analog switch
5
connected to this output terminal. Accordingly, a voltage of a video bus line connected to the analog switch
5
is supplied to the corresponding signal line and the video bus line is charged. The analog switch
5
is then turned OFF at the time T
13
. The voltage charged in the signal line via the analog switch
5
just before the analog switch
5
is turned OFF is held in the signal line.
Currently, signal line driving methods include, besides the frame inversion driving method in which the polarity of voltage relative to a reference voltage is inverted frame by frame in order to avoid deterioration of liquid crystal display device, a V-line inversion driving method in which the polarity of voltage relative to the reference voltage is inverted by every signal line, and an H-line inversion driving method in which the polarity of voltage relative to the reference voltage is inverted by every one or more horizontal lines. The V-line driving method, and the H-line driving method are combined with the frame inversion driving method to lower the flicker.
FIG. 3
is a timing chart showing the timings of several devices of the signal line driving circuit of
FIG. 1
when the H-line inversion driving is carried out. In descending order, the timings of control signals inputted to control terminals of the analog switches
5
, the voltage level of the video bus lines L
1
-Lm, and the voltage level of the signal lines are shown. In
FIG. 3
, the voltage levels of the positive polarity side for displaying white is 5.5V and that for displaying black is 9.5V, and the voltage levels of the negative polarity side for displaying white are 4.5V and that for displaying black is 0.5V.
FIG. 3
shows that a black-level voltage is held from the time T
11
till the next horizontal line period. The period from T
12
to T
13
is a horizontal blanking period. After the time T
13
, display of the next horizontal line is begun.
When the H-line inversion driving is carried out, for example, a polarity of the signal line voltage becomes larger or smaller than the reference voltage. Because of this, from the time T
13
onward, the pixel voltage with negative polarity relative to the reference voltage is supplied to the video bus line.
FIG. 3
shows an example in which two adjacent horizontal lines are set to voltages corresponding to black.
Thus, when the H-line inversion driving is carried out, the polarity of the signal line voltage should be inverted relative to the reference voltage at a predetermined timing in one frame period. Accordingly, the level of voltage supplied to signal lines via the bus line should be considerably changed. For example, when the voltage level of two adjacent horizontal lines is changed from that for black in the positive polarity to that of black in the negative polarity, the difference in voltage is:
9.5V-0.5V=9V.
However, in the block sequence driving shown in
FIG. 1
, as the period in which the analog switch
5
is on is only some hundreds nsec, it is very difficult to dramatically change the voltage level of the video bus lines and the signal lines during this period.
If the voltage level of two adjacent horizontal lines is changed from that for white in the positive polarity to that of white in the negative polarity, the difference in voltage is:
5.5V-4.5V=1.0V.
As this difference is quite lower than that of black level (9.0V), it is rather easy to change the voltage of the video bus lines and the signal lines.
As mentioned above, when the H-line inversion driving is carried out in a conventional liquid crystal display device, the polarity of voltage of signal lines should be changed by a predetermined number of horizontal lines. The closer to black a color is, the higher the difference in voltage level between the positive polarity and the negative polarity becomes. As a result, errors in writing to signal lines would easily occur for such a color, thereby causing display faults such as a contrast deterioration.
On the other hand, when the V-line inversion driving is carried out, because the polarity of voltage is never inverted by every single horizontal line, decline of contrast due to the write shortage of the signal line voltage by the above-mentioned polarity inversion does not occur. However, the horizontal line written just after the vertical blanking period is finished is supplied with a voltage, the polarity of which is inverted relative to that of a just previous horizontal line. Because of this, the closer to black a color is, the more likely the write shortage to the signal lines is. As a result, the display quality deteriorates. Specifically, the contrast becomes lower than the other horizontal scanning lines, or the thin blight lines occurs on the display region.
As a method for avoiding deterioration of display quality due to errors of signal line voltage, Japanese Patent Laid-Open Publication No. 6-20276 discloses a technique for precharging signal line capacitances during the blanking period in order to reduce the influence of change in voltage of signal lines on pixels.
FIG. 4
is a circuit diagram of a liquid crystal display device disclosed in the above-mentioned publication. The display shown in
FIG. 4
has a signal line driving circuit
60
including a first register group
60
a
and a second register group
60
b
. In a blanking period, all of the TFTs
61
connected to signal lines S are turned ON by the first register group
60
a
, and all of the TFTs
62
are turned ON by a shift pulse outputted from the second register group
60
b
, thereby precharging each signal lines via reset signal lines
63
.
However, the above-mentioned displ
Kabushiki Kaisha Toshiba
Patel Nitin
Shankar Vijay
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