Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2005-06-06
2009-10-13
Awad, Amr (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S690000
Reexamination Certificate
active
07602367
ABSTRACT:
A flat display panel comprises a matrix array of pixels that displays an image, a controller that receives a video signal supplied externally along with a horizontal sync signal defining a horizontal scanning period and a vertical sync signal defining a vertical scanning period, a driver circuit that is controlled by the controller and writes the video signal and non-video signal into each row of pixels in each vertical scanning period, and an insertion timing setting section that controls a write timing of the non-video signal to synchronize with a write timing of the video signal. The insertion timing setting section is configured to count the number of horizontal sync signals supplied within the vertical scanning period defined by each vertical sync signal, and then determine the write timing of the non-video signal based on a result of counting.
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Awad Amr
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Toshiba Matsushita Display Technology Co., Ltd.
Willis Randal
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