Flat display driving circuit for a display containing margins

Details Flat display driving circuit for a display containing margins Flat display driving circuit for a display containing margins

1988-09-27

1990-10-23

Oberley, Alvin

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340805, G09G 320

Patent

active

049655639

ABSTRACT:
A flat display driver in a drive circuit for driving a flat display including a memory storing data to be displayed on a display panel of a line scan type having a two-dimensional structure constituted with N rows by M columns, an address generator for generating a read address of the memory and a line clock signal, a data output terminal for supplying the display panel with data read from the memory, and a line clock signal output terminal for supplying the line clock signal from the address generator to the display panel. The memory is loaded at least with display data constituted with K rows by M columns (K<N) and the driver further includes a margin scan detect device in which respective margin lines ((N-KO/2) in upper and lower portions of the display panel are set in advance for receiving and for counting the line clock from the address generator, thereby detecting a margin detect signal when the count in equal to a value corresponding to the margin line and a margin display output device operative in response to an input of the margin detect signal from the margin detect device for outputting a margin display signal to the display panel.

REFERENCES:
patent: 4656470 (1987-04-01), Saka
patent: 4740786 (1988-04-01), Smith
patent: 4748444 (1988-05-01), Arai
patent: 4759609 (1988-07-01), Clerc
patent: 4778260 (1988-10-01), Okada et al.
patent: 4804952 (1989-02-01), Hara
patent: 4824212 (1989-04-01), Taniguchi
Hitachi Microcomputor System, LCD Timing controller (LCTC) HD 63645F/HD 64645F User's Manual.

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