Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Patent
1996-03-29
2000-02-08
Chow, Dennis-Doon
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
345208, 345213, G09G 328
Patent
active
060232587
ABSTRACT:
The present invention provides a flat display including a high-speed arithmetic logic facility so that, even when a data signal for a first line follows immediately after a frame start signal, the display displays an image with stable display quality quickly. For controlling driving signals in a flat display, each sub-frame of a temporally-segmented frame comprises at least an initialization period S1' during which a display screen is initialized, an addressing period S2 during which a plurality of cells are selected and written with display data, and a sustaining discharge period S3 during which the cells which contain display data are discharged so as to emit light for a given period of time. The flat display includes an initialization start time control unit 100 that detects the input of a display start signal V.sub.SYNC for one frame, and controls an initialization start time ST of the initialization period S1' so that the ST will precede an instant of input of a frame start signal V.sub.SYNC.
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Kaneko Keiichi
Kuriyama Hirohito
Ueda Toshio
Yamamoto Akira
Chow Dennis-Doon
Fujitsu Limited
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