Flat-cell nonvolatile semiconductor memory

Details Flat-cell nonvolatile semiconductor memory Flat-cell nonvolatile semiconductor memory

2002-03-04

2003-06-10

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

Reexamination Certificate

active

06577536

ABSTRACT:

This application incorporates by reference Taiwanese application Serial No. 90129597, Filed Nov. 29, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to the semiconductor memory, and more particularly to the flat-cell nonvolatile semiconductor memory.
2. Description of the Related Art
The need for larger capacity of the nonvolatile semiconductor memory grows rapidly, and thus a high-density semiconductor memory is required. Flat-cell semiconductor memory is the one that can achieve high density and can be also easily manufactured.
FIG. 1A
is a circuit diagram of the Nth bank of the read only semiconductor memory from U.S. Pat. No. 5,117,389. The memory includes some banks, and uses bank-selecting switches for selecting one of the banks. Each bank includes a memory cell array, and each memory cell is used for data storage. Each memory cell is a transistor, whose threshold voltage Vt depends on the content of the cell. Bank word line BWL
N
is used to select the Nth bank of the memory. Word lines SWL
N1
~SWL
NM
are used to select one row of the memory cell array. Then, bit lines SBL
N
and SBR
N
are used to select a memory cell for reading.
FIG. 1B
shows a diagram while reading the memory cell D. First, enable bank word lines BWL
N
and bit line SBR
N
, then the current flows from bit line BL
N
to transistor M
2
, transistor D, transistor R
5
, transistor M
3
and back to ground line VG
N+1
. The current for reading a memory cell flows through four transistors in this case. And three selecting signals are needed.
The sources and drains of the memory cells are formed by diffusion layers. The sources/drains of the memory cells at the same column constitute a sub-bit line. A word line is formed by polysilicon, and the polysilicon also constitutes the gates of the memory cells. A memory cell with a ROM code has higher threshold voltage, and the ROM code is supplied depending on the content of the memory cell. There is no need of field oxide layer between memory cells and thus the layout is flat. The flat-type layout reduce the area of the memory. However, a field oxide layer is needed between the bank selection switches, such as M
1
and M
2
. The manufacture process with an oxide layer costs more, and the area of the memory is larger.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved and simplified flat-cell nonvolatile semiconductor memory. The semiconductor memory includes a plurality of units. Each unit includes word lines, a main bit line, a ground line, sub-bit lines, memory cell columns, and bank-selecting switches. Word lines are disposed in parallel, and the main bit line and the ground line cross the word lines. Sub-bit lines are disposed substantially in parallel to the main bit lines. Each memory cell column includes a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines. The bank-selecting switches are used to select one of the memory cell columns.
The first one of the bank-selecting switches is disposed between the main bit line and the fourth sub-bit line. The second of the bank-selecting switches is disposed between the main bit line and the second sub-bit line. The third of the bank-selecting switches is disposed between the ground line and the fifth sub-bit line. The fourth of the bank-selecting switches is disposed between the ground line and the third sub-bit line. The fifth of the bank-selecting switch is disposed between the ground line and the third sub-bit line. The sixth bank-selecting switch is disposed between the ground line and the first sub-bit line.
Wherein, the second, third, and fourth bank-selecting switches are controlled by a first selecting signal, and the first, fifth, and sixth bank-selecting switches are controlled by a second selecting signal.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following detailed description is made with reference to the accompanying drawings.


REFERENCES:
patent: 5117389 (1992-05-01), Yiu
patent: 5966327 (1999-10-01), Jo
patent: 6084794 (2000-07-01), Lu et al.
patent: 6157580 (2000-12-01), Kohno
patent: 6278649 (2001-08-01), Lee et al.
patent: 6430079 (2002-08-01), Shiau

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