Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-04-26
2002-11-12
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S156000
Reexamination Certificate
active
06480135
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flash type analog-to-digital converter of a plurality of reference voltages different by predetermined voltage steps and comparing the related plurality of reference voltages with an analog input signal in parallel to convert the analog input signal to a digital code of predetermined bit width.
2. Description of the Related Art
As an ultra-high speed analog-to-digital converter (hereinafter referred to as an “ADC”), a configuration known as a flash type has been used. Its prototype goes back to U.S. Pat. No. 4,276,543 (filed on Mar. 19, 1979).
A flash ADC, in principle, comprises (2
N
−1) comparators to generate N-bit output. Each comparator has two inputs. One is common to all comparators and is connected to the analog signal input. The other input of each comparator is connected to an input reference potential which differs by 1 LSB from adjacent one. The input analog signal is first converted to a code called a “thermometer code” by the comparator array. This terminology comes from the region of comparators of “1” indicating that the input signal is higher than the reference voltage increases or decreases like an alcohol thermometer in accordance with the analog input voltage.
The thermometer code is converted to an impulsive code which has only “1” at the border of the thermometer code by a so-called differentiation circuit, then is converted to a final binary code. The last encoder (often referred as a “decoder” in literature quite confusingly) usually employs a ROM structure using a wired OR (WOR).
Below, an explanation will be given of a 4-bit ADC by using logic formulae.
The outputs of the comparators are represented by C[i] (i=1, 2, . . . , 15). This C[i] array forms a thermometer code. In the thermometer code, when an input level is in a semi-closed interval [i, i+1), the comparator outputs from C[1] to C[i] are “1”, and the remaining comparator outputs, that is, C[i+1] to C[15], are “0”.
The differentiation circuit is expressed by the following formula (1).
D[i]=C[i]&!C[i+1] (1)
(i=1, 2, . . . , 14)
Here, “&” denotes a logical multiplication, and “!” denotes a bit inversion.
The encoder binary output is expressed by the following formula (2).
ADB
[
3
:
0
]
=
(
D
[
1
]
&
0001
′
′
)
|
(
D
[
2
]
&
0010
′
′
)
|
(
D
[
3
]
&
0011
′
′
)
|
(
D
[
4
]
&
0100
′
′
)
|
(
D
[
5
]
&
0101
′
′
)
|
(
D
[
6
]
&
0110
′
′
)
|
(
D
[
7
]
&
0111
′
′
)
|
(
D
[
8
]
&
1000
′
′
)
|
(
D
[
9
]
&
1001
′
′
)
|
(
D
[
10
]
&
1010
′
′
)
|
(
D
[
11
]
&
1011
′
′
)
|
(
D
[
12
]
&
1100
′
′
)
|
(
D
[
13
]
&
1101
′
′
)
|
(
D
[
14
]
&
1110
′
′
)
|
(
D
[
15
]
&
1111
′
′
)
(
2
)
Here, ‘0001’ etc. are 4-bit constants, and “ADB” is the 4-bit ADC output of the binary code format. Also, “&” denotes a logical multiplication (AND), and “|” denotes a logical sum (OR). Each D[i] of equation (1) is extended to 4 bits and applied in equation (2).
An example of the configuration of a conventional parallel type analog-to-digital converter is shown in FIG.
10
.
A resistor string equivalently expressed by a series connection of for example 16 resistor elements R
16
, R
15
, . . . , and R
1
is provided between the reference voltages VRT and VRB. Connection points of the resistor elements in the resistor string are connected to inverting terminals (−) of 15 comparators C
15
, C
14
, . . . , and C
1
. Analog signal Vin is input to non-inverting terminals (+) of the comparators C
15
, C
14
, . . . , and C
1
.
The differentiation circuit is comprised of AND gates A
15
, A
14
, . . . , and A
1
. According to equation (1), 14 AND gates of A
14
, A
13
, . . . , and A
1
are connected to corresponding comparator outputs C[i] and the invert of C[i+1] respectively. The output C[15] of the comparator C
15
of the most significant bit is input to the two input terminals of the AND gate A
15
, whereby the comparator C
15
acts as a buffer.
The encoder ECD
1
comprises a ROM circuit of for example the WOR configuration. The double circle marks in the figure indicate elements functioning as OR logic inputs from the outputs D[i] of the differentiation circuit.
The outputs D[i] of the differentiation circuit (AND gates A
15
, A
14
, . . . , and A
1
) are input to the encoder ECD
1
and converted to a 4-bit binary code format digital signal ADB [3:0] according to equation (2).
The most significant bit (MSB) of ADB [3:0], that is, ADB[3], is found in the OR logics of the outputs D[15], D[14], . . . , and D[8] of the differentiation circuit. Similarly, ADB[2] is found in the OR logics of the outputs D[15], D[14], D[13], D[12], D[7], D[6], D[5], and D[4] of the differentiation circuit, while ADB[1] is found in the OR logics of the outputs D[15], D[14], D[11], D[10], D[7], D[6], D[3], and D[2] of the differentiation circuit. Also, the least significant bit (LSB) of ADB [3:0], that is, ADB[0], is found in the OR logics of the outputs D[15], D[13], D[11], D[9], D[7], D[5], D[3], and D[1] of the differentiation circuit.
In an ADC of the configuration, assume for example the level of the now input analog signal Vin is at the seventh level among the 15 voltage ranges (hereinafter simply referred to as levels) obtained by dividing equally into 16 intervals from 16 resistor elements, that is, the input level is in the semi-closed interval [7,8). At this condition, seven comparator outputs C[1], C[2], . . . , and C[7] indicate 1, while the remaining eight comparator outputs C[8], C[9], . . . , and C[15] indicate 0. So that, the only A
7
AND gate output D[7] in the differentiation circuit indicates 1, while all of the remaining AND gate outputs indicate 0. Hence in the OR logic of the encoder ECD
1
, only the most significant bit becomes 0, so ADB[3:0]=‘0111’ is the output of the ADC.
At the next instant, let assume the input level slightly rises to the eighth level, that is, it shifts to the semi-closed interval [8,9). At this time, in addition to the seven comparator outputs C[1], C[2, . . . , and C[7], the eighth comparator output C[8] also turns to 1. As a result, the AND gate output of the state
1
in the differentiation circuit moves from D[7] to D[8]. Accordingly, the OR logic result of the encoder ECD
1
becomes 1 only at the most significant bit. The output ADB[3:0] of the ADC changes from ‘0111’ to ‘1000’.
In flash type ADC, this parallel mechanism converts the voltage level of the analog input signal to a 4-bit digital code very fast.
The problem of this encoding scheme resides in that, if there is a bubble error which is an invalid thermometer code, or at the occurrence of a metastable state, a large error called “sparkle” arises. For example, when the input level is around the seventh level, if not only C[1] to C[7], but also C[9] become 1 then a bubble error occurs. In this case
Kananen, Esq. Ronald P.
Radar Fishman & Grauer PLLC
Sony Corporation
Wamsley Patrick
LandOfFree
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