Flash synchronized gated sample clock generator

Details Flash synchronized gated sample clock generator Flash synchronized gated sample clock generator

1989-02-14

1990-03-13

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

328 72, 340814, 358148, H04N 505

Patent

active

049088424

ABSTRACT:
Digital flash synchronization for instantaneously re-phasing an asynchronous clock signal with a second signal from a desired source is disclosed. Included is a delay line with a multiplicity of equally spaced taps for presenting a multiplicity of clock signals at different phases. A first register is included to receive the second signal as a trigger and to store a snap-shot of the clock signals from the taps of the delay line and the undelayed clock signal in response to the second signal. A look-up table is used to identify the phase of the clock to be selected that agrees most closely with the second signal from the snap-shot of signals stored in the first register. Next, a multiplexer is used to select the preliminary re-phased clock signal from the clock signal and each of the signals at the taps of the delay line in response to the identified phase from the look-up table. A delay is then provided to delay the second signal by the propagation delay of the look-up table and the multiplexer. This delay is followed by a second register that receives the delayed second signal and produces the delayed second signal in response to the preliminary re-phased clock signal. The delayed second signal from the second register and the preliminary re-phased clock signal from the multiplexer are applied to an OR gate to produce the final re-phased clock signal. Modifications of the basic embodiment are provided to handle a range of clock frequencies and to minimize the size of the delay line and the look-up table.

REFERENCES:
patent: 4386323 (1983-05-01), Jansen
patent: 4546350 (1985-10-01), Tanaka

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