Flash output LSSD latch

Details Flash output LSSD latch Flash output LSSD latch

1998-02-05

2000-02-01

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327203, H03K 3356

Patent

active

060207728

ABSTRACT:
A two stage latch or shift register latch with very reduced propagation delay in the second stage, that may be used for LSSD type integrated circuits. The two stage register includes a first stage receiving and latching data. The first stage may also include a scan input for scanning in test data. The data is passed to a second stage which provides the received data as an output and latches the output. The preferred second stage includes a pair of cross coupled inverters, and a complementary clock stage. The complementary clock stage selectively passes the received data from the first stage to the output and, then, the second latch latches the output.

REFERENCES:
patent: 4939384 (1990-07-01), Shikata et al.
patent: 5032783 (1991-07-01), Hwang et al.
patent: 5059828 (1991-10-01), Tanagawa
patent: 5539336 (1996-07-01), Nguyen et al.
patent: 5598120 (1997-01-01), Yurash
patent: 5610927 (1997-03-01), Segars
patent: 5633606 (1997-05-01), Gaudet et al.
patent: 5656962 (1997-08-01), Banik
patent: 5668490 (1997-09-01), Mitra et al.
patent: 5706627 (1998-01-01), Gregor et al.
patent: 5767716 (1998-06-01), Ko

Affiliated with

Also associated with

Rating

Flash output LSSD latch does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flash output LSSD latch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash output LSSD latch will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-940627