Flash non-volatile memory

Details Flash non-volatile memory Flash non-volatile memory

1993-09-21

1995-04-11

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Plural blocks or banks

365218, 365900, 395425, 395400, G11C 1602

Patent

active

054065291

ABSTRACT:
A flash-erase memory includes a plurality of blocks accessible by a processor and, in association with each block, a block ID representing an address (RBA) specified by the processor upon writing, a revision code (RC) indicating how many times the processor performed writing using the same RBA, and an erase count (EC) indicating the number of times of erasing of this block are stored. Writing is performed to a writable block having the minimum erase count, and if there is a different block having the same block ID as the address specified by the processor, its revision code is updated and used as a revision code of the written block, and the different block is erased and its erase count is updated.

REFERENCES:
patent: 4638430 (1987-01-01), Perra et al.
patent: 5138580 (1992-08-01), Farrugia et al.
patent: 5297103 (1994-03-01), Higuchi
IEEE Spectrum, Dec. 1989, pp. 30-33, entitled "Flash memories: the best of two worlds," by Richard D. Pashley and Stefan K. Lai of Intel Corporation.

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