Flash memory with shortened erasing operation time

Details Flash memory with shortened erasing operation time Flash memory with shortened erasing operation time

2005-02-15

2005-02-15

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220

Reexamination Certificate

active

06856553

ABSTRACT:
A flash memory having a nonvolatile memory cell, includes a plurality of banks each having a plurality of sectors, an erasing voltage generator circuit and a writing voltage generator circuit, wherein while an applying an erase pulse to a sector to be erased in a first bank, an erasing control is performed by, a pre-writing control is concurrently performed by applying a writing pulse to a sector to be erased in a second bank.At the time when erasing control of the sector to be erased in a first bank is finished, pre-writing control of the sector to be erased in a second bank is finished or partially finished, and thus the time required for erasing operations of the first and the second bank can be reduced.

REFERENCES:
patent: 5748528 (1998-05-01), Campardo et al.
patent: 5847994 (1998-12-01), Motoshima et al.
patent: 5949716 (1999-09-01), Wong et al.
patent: 6088264 (2000-07-01), Hazen et al.
patent: 6345000 (2002-02-01), Wong et al.
patent: 6469928 (2002-10-01), Takata

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