Static information storage and retrieval – Floating gate – Particular connection
Patent
1996-12-09
1998-06-30
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular connection
36518511, 36518529, G11C 1606
Patent
active
057743967
ABSTRACT:
The invention provides a flash memory with row redundancy. The memory includes an input terminal to receive an address and a command signal. A plurality of flash memory arrays are arranged as blocks, where each block includes a plurality of transistors organized in rows and columns and having respective wordlines, bitlines and a sourceline. A wordline decoder is coupled to the input terminal and a portion of the plurality of blocks and configured to decode a portion of the address and to receive a control signal to selectively apply a predetermined voltage to a wordline. A bitline decoder is coupled to the input terminal and to the plurality of blocks and configured to decode a portion of the address and to selectively pass a predetermined bitline to an output terminal. A match circuit is coupled to the input terminal and to a portion of the plurality of blocks and configured to decode a portion of the address and to receive the control signal to selectively apply a predetermined voltage to a wordline. A control circuit is coupled to the wordline decoder and the match circuit and configured to selectively activate one of the wordline decoder and the match circuit by the control signal. Advantages of the invention include improved row redundancy for wordline replacement and block replacement.
REFERENCES:
patent: 5233559 (1993-08-01), Brennan, Jr.
patent: 5426608 (1995-06-01), Higashitani
patent: 5596535 (1997-01-01), Mushya
patent: 5621690 (1997-04-01), Jungroth
Hsu Fu-Chang
Lee Peter W.
Tsao Hsing-Ya
Aplus Integrated Circuits, Inc.
Mai Son
Nelms David C.
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