Flash memory with pre-detection for data loss

Details Flash memory with pre-detection for data loss Flash memory with pre-detection for data loss

2003-05-15

2004-11-16

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185210, C365S185330

Reexamination Certificate

active

06819589

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a nonvolatile memory device, and, more particularly, to a method and a circuit to prevent data retention errors in a nonvolatile memory device.
(2) Description of the Prior Art
Nonvolatile memory is a critical component in microprocessor-based systems. Maximum system flexibility is achieved through the use of nonvolatile, re-programmable memories such as flash memory. By storing operating programs or key system parameters in flash memories, system performance can be rapidly, and permanently, changed in the field.
Referring now to
FIG. 1
, an exemplary flash memory cell is illustrated in schematic
22
and cross sectional
10
forms. The flash cell
10
is a form of a MOS transistor having a source
16
and drain
14
formed in a substrate region
12
. A complex gate is formed comprising a control gate (CG)
20
and a floating gate (FG)
18
. The transistor may be operated by biasing the control gate
20
, drain
14
and source
16
as is well known in the art. The floating gate
18
comprises a conductive region electrically isolated from the substrate
12
by a first dielectric region
17
and electrically isolated from the control gate
20
by a second dielectric region
19
. As in any MOS transistor, the device is turned ON when a sufficient bias is applied to the control gate
20
to create a channel region of to carry charge from the drain
14
to the source
16
. The necessary control gate bias is defined as a threshold voltage (V
TH
) . As is well known in the art, charge, in the form of electrons, may be injected into or out from the floating gate
18
. The presence of charge on the floating gate
18
will alter the V
TH
of the device
10
. This fact may be used to create a digital memory cell where a first state is defined by a large presence of charge and a second state is defined by an absence of charge. To program or erase the state of the cell
10
, relatively large voltage biases may be applied to a combination of control gate
20
, drain
14
, and source
16
to cause the injection of charge into the floating gate
18
or to cause the removal of charge from the floating gate
18
. To read the state of the cell
10
, the control gate
20
may be biased to a voltage whereby the device should be ON or should be OFF, depending on the charged state of the floating gate. A voltage bias from drain
14
to source
16
will cause a current to flow if the device is ON. This current flow, or the absence or this current flow, may be detected to determine to state of the cell
10
as is well known in the art.
Referring now to
FIG. 2
, an exemplary diagram of a circuit for the reading a flash cell is illustrated. A section
30
of an integrated circuit device is illustrated showing an array
32
of nonvolatile cells. A particular cell
34
of the memory array is selected by asserting its wordline WL
42
and bit line BL by methods well known in the art. The WL voltage is connected to the control gate of the cell
34
and the BL voltage V
BL
is connected to the drain. The cell current I
CELL
is the drain-to-source current (I
DS
) of the cell
34
. If the cell threshold voltage (V
TH
) exceeds the WL voltage, then the cell
34
will be OFF and I
CELL
will be very small. If the cell V
TH
is less than the WL voltage, then the cell
34
will be ON and I
CELL
will be much larger.
To determine the relative V
TH
, and therefore the cell
34
logic state, a reference cell
36
is used. The reference cell
36
comprises a comparable flash device having a fixed V
TH
. The reference cell
36
control gate is biased to a reference voltage V
REF
and the drain is biased to a bit line voltage V
BL
. A reference current I
REF
is generated. A comparitor
40
is used to compare the reference current I
REF
with the cell current I
CELL
. The comparitor output
46
is the decoded CELL STATE, which is either high or low.
The logic state of each cell in a flash memory array is typically tested at the factory following programming. Theoretically, the isolated floating gate and the solid state character of the device should create very long data retention times. However, it is known in the art there is a statistical distribution to the retention capabilities of cells and that some data cells will exhibit substantially shorter data retention times than the average. It is further found that these leaky cells, have a non-constant amount of floating gate charge over time. If, for example, a cell is fully charged during programming, then the cell will initially read the correct cell state of ‘X’ but later will read an incorrect cell state of ‘Y’ when the floating gate has become sufficiently discharged. In the field, this shortened data retention cell may create a single bit failure, as opposed to a grouped or burst failure. In certain applications, especially automotive or industrial control systems, a product malfunction due to such a memory error is a serious matter. Therefore, it is of great advantage to prevent such memory errors.
Several prior art inventions relate to methods to detect bit errors in nonvolatile memories. U. S. Pat. No. 6,483,745 B2 to Sacki teaches a method and a circuit to detect and to correct soft errors in a nonvolatile cell. The cell is read three times using three different reference transistors. One reference is the standard reading reference, one reference is for a programmed state threshold, and one reference is for an erase state threshold. By comparing the results of each of the three reads, the cell state and margin can be determined. U.S. Pat. No. 6,049,899 to Auclair et al describes a method and a circuit to detect soft errors in a nonvolatile memory array. Cells are read using variable control gate voltages or using variable reference currents to thereby assess the state and margin of the cell. Cells with inadequate margin are refreshed. U.S. Pat. No. 6,525,960 B2 to Yoshida et al discloses a method and a circuit to write a multiple value, nonvolatile memory array. A method to correct erratic cells is disclosed.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable integrated circuit device.
A further object of the present invention is to provide a method to detect and to correct weak cell states in a nonvolatile memory device.
A yet further object of the present invention is to prevent bit errors in a nonvolatile memory device.
A yet further object of the present invention is to selectively refresh memory cells in a nonvolatile memory device in an efficient method.
A yet further object of the present invention is to provide a method to continuously detect weak cell states.
A yet further object of the present invention is to provide a method for multiple level nonvolatile memory as well as for binary nonvolatile memory.
Another further object of the present invention is to provide a nonvolatile memory device capable of detecting weak cell states.
In accordance with the objects of this invention, a method to detect and to correct a weakly programmed cell in a nonvolatile memory device is achieved. The method comprises providing a plurality of nonvolatile memory cells. A means to read a selected cell compares the performance of the selected cell with the performance of a reference cell. A read state of the selected cell is high if the selected cell exceeds the reference cell. The read state of the selected cell is low if the selected cell exceeds the reference cell. A first read state is obtained by reading the selected cell with the reference cell biased to a first value. A second read state is obtained by reading the selected cell with the reference cell biased to a second value that is greater than the first value. The selected cell is flagged as weakly programmed, high if the first and second read states do not match. A third read state is obtained by reading the selected cell with the reference cell biased to a third value that is less than the first value. The selected cell is flagged as weakly programmed, low

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