Flash memory with high speed erasing structure using thin oxide

Details Flash memory with high speed erasing structure using thin oxide Flash memory with high speed erasing structure using thin oxide

1997-08-22

1999-06-22

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular biasing

36518528, 36518529, 36518523, G11C 1600

Patent

active

059148969

ABSTRACT:
A flash memory with a high speed erasing structure includes a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline. A wordline decoder is coupled to the wordlines and configured to selectively apply voltages to the wordlines to perform procedures on the flash transistors, where the procedures include a read procedure, an erase procedure and a program procedure. During the erase procedure, the wordline decoder is configured to apply a first increasingly negative voltage in a first voltage range to at least one selected wordline until a first threshold voltage is met, then to apply a second increasingly negative voltage in a second voltage range to the selected wordline and to simultaneously apply a third negative voltage in a third voltage range to at least one deselected wordline. Another embodiment of the invention increases the selected sourceline voltage to achieve a high voltage differential between the gate and source of flash transistors selected to be erased. In another second embodiment, the wordline decoder is constructed from thin oxide and thick oxide semiconductor devices. Thick oxide devices are used in the wordline driver, which allows an increased voltage differential to be applied to the wordlines without damaging the wordline driver. Advantages of the invention include a fast erasing procedure due to the increased voltage differential applied between the gate and source of flash transistors selected to be erased.

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