Flash memory with DDRAM interface

Details Flash memory with DDRAM interface Flash memory with DDRAM interface

2001-08-30

2003-05-27

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S233100, C365S189050

Reexamination Certificate

active

06570791

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to a non-volatile memory interface.
BACKGROUND OF THE INVENTION
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus. SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
Advances in DRAM interfaces has resulted in double data rate (DDR) DRAMs. These memory devices provide data communication that is synchronized to both rising and falling edges of a clock signal. While DDR DRAMs provide for fast data communications, the data is stored in a volatile manner.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory that can communicate at fast DRAM speeds.
SUMMARY OF THE INVENTION
The above-mentioned problems with non-volatile memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a flash memory comprises an array of non-volatile memory cells, data connections, and output circuitry to provide output data on the data connections on rising and falling edges of a clock signal.
In another embodiment, a flash memory comprises an array of non-volatile memory cells, data connections, a clock signal connection to receive a clock signal, and output circuitry to provide output data on the data connections on rising and falling edges of the clock signal. Input circuitry is provided to receive input data on the data connections on rising and falling edges of the clock signal.
A method of reading a flash memory comprises providing a read command, providing memory cell addresses, reading first and second data words from non-volatile memory cells, outputting the first data word on a rising edge of a clock signal, and outputting the second data word on the falling edge of the clock signal.
Another method of reading a flash memory comprises reading first and second data words from non-volatile memory cells, outputting the first data word on a rising edge of a clock signal, and outputting the second data word on the falling edge of the clock signal.


REFERENCES:
patent: 5903496 (1999-05-01), Kendall et al.
patent: 6043694 (2000-03-01), Dortu
patent: 6100733 (2000-08-01), Dortu et al.
patent: 6130853 (2000-10-01), Wang et al.
patent: 6134180 (2000-10-01), Kim et al.
patent: 6154419 (2000-11-01), Shakkarwar
patent: 6166970 (2000-12-01), Yun
patent: 6201760 (2001-03-01), Yun et al.
patent: 6215710 (2001-04-01), Han et al.
patent: 6215722 (2001-04-01), Park
patent: 6215726 (2001-04-01), Kubo
patent: 6233199 (2001-05-01), Ryan
patent: 6310814 (2001-10-01), Hampel et al.
patent: 6327216 (2001-12-01), Ryan
patent: 6336174 (2002-01-01), Li et al.
patent: 6343046 (2002-01-01), Matsui

Affiliated with

Also associated with

Rating

Flash memory with DDRAM interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flash memory with DDRAM interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory with DDRAM interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3080250