Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-05-17
2001-03-13
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185290, C365S185330
Reexamination Certificate
active
06201736
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flash memory having a function that can be performed by an external command for copying and transferring data in the memory and for combining data from a plurality of cell blocks.
2. Related Art
A flash memory is a non-volatile memory that uses transistors having floating gates. Anon-volatile memory that uses floating gates was first developed as EPROM which could be totally erased by irradiating it with ultraviolet rays, however after that, by making it possible to erase the memory electrically, it evolved into a flash memory. Inside the flash memory is divided into a plurality of cell blocks, and it is erased together in units of cell blocks.
The flash memories that are currently popular on the market are capable of holding data when the power is OFF. For example, they are used as the medium for storing image data of a digital camera. In response to a “Write” command or “Erase” command from a memory controller, the flash memory automatically writes or erases data. Therefore, a control circuit is built in for decoding external commands and for performing the processes that correspond to those commands. This control circuit controls internal operations for “Read” commands as well.
For example, when a “Write” command is given for an erased cell block, specified write pulses are applied to memory cells corresponding to the write data and address, so that a charge is injected in the floating gate, and then write verify is performed to check the threshold voltage after the charge has being injected. This series of processes is then repeated. Also, when an “Erase” command is given, pre-programming (the aforementioned write process) is performed for cells that have not been written to, then an erase pulse is applied to all of the cell blocks together and erase verify is performed to check the threshold voltage. This series of processes is then repeated. Normally, writing is performed in 1-byte units.
However, the prior commands are designed for only writing data or erasing cell blocks. As mentioned above, it is expected that flash memories will be more widely used in the future for uses such as the storage medium for image data of digital cameras or as the storage medium for other portable terminals. In that case, for example, a function that would make it possible to copy data from one cell block to another cell block, or to transfer the data of one cell block to another cell block, or furthermore, to transfer part of the data from many cell blocks to another cell block and combine that data, is desired.
In prior flash memories with only a command function for writing or erasing, it is necessary for a memory controller to perform very complicated controls. For example, to copy within the memory device, first the data of the cell block to be copied must be read externally and stored by the system, then, it is necessary to write the externally stored data, while specifying the address of the cell block where the data are to be copied. Also, when the destination cell block is already written some data, it is necessary to first give an “Erase” command for the destination cell block.
When copying within the memory device, it is necessary for the system to perform the complicated processes mentioned above, which requires much time and steps.
Moreover, in the testing process of the memory, identical data may be written to all of the cell blocks and then read and checked whether written properly. In this case, it is necessary to repeat identical write control for several cell blocks, and in order to complete the writing to all of the blocks of the memory, it requires a large command instruction cycles which in turn require many processes and time.
SUMMARY OF THE INVENTION
The objective of the present invention is to provide a flash memory that is capable of copying, transfer and combining data in the memory with one or a few external commands, which could not be done in a prior flash memory.
In order to accomplish this objective, one example of the present invention provides a flash memory, having a plurality of non-volatile memory cells, comprising:
a plurality of cell blocks having said plurality of non-volatile memory cells,
a data latch circuit, connected to said cell blocks, for storing data that is read from or written to a selected cell block, and
a control circuit for, in response to an external copy command, erasing a copy destination cell block, reading data from a copy source cell block to store the data in said data latch circuit, and writing the stored data to said copy destination cell block.
In the aforementioned flash memory, when the system gives the address of the copy source cell block and the address of the copy destination cell block, checking and erasing of the copy destination cell block required for copying, reading of data from the copy source cell block and writing that data to the copy destination cell block are performed automatically inside the memory. In addition to the conventional writing and erasing controls, the control circuit responds to a macro copy command and performs the control by employing the conventional read, write and erase sequences.
Another example of the present invention provides a flash memory, having a plurality of non-volatile memory cells, comprising:
a plurality of cell blocks having said plurality of non-volatile cell memory cells,
a data latch circuit, connected to said cell blocks, for storing data that is read from or written to a selected cell block, and
a control circuit for, in response to an external transfer command, erasing a transfer destination cell block, reading data from a transfer source cell block to store the data in said data latch circuit, writing the stored data to said transfer cell block and erasing said transfer source cell block.
In the aforementioned flash memory, when the system gives the address of the transfer source cell block and the address of the transfer destination cell block, all necessary processes are performed automatically inside the memory. Therefore, the control unit responds to a transfer command, and in addition to the aforementioned copy process, it also erases the transfer source cell block.
Furthermore, another example of the present invention provides a flash memory, having a plurality of non-volatile memory cells, comprising:
a plurality of cell blocks having said plurality of non-volatile cell memory cells,
a data latch circuit, connected to said cell blocks, for storing data that is read from or written to a selected cell block, and
a control circuit for, in response to an external combine command, erasing a transfer destination cell block, reading data from a first transfer source cell block to store the data in said data latch circuit, writing the stored data in said transfer destination cell block, reading data from a second transfer source cell block to store the data in said data latch circuit, writing the stored data to said transfer destination cell block, and erasing said first and second transfer source cell blocks.
In the aforementioned flash memory, when the system gives a transfer command and a plurality of addresses of the transfer source cell blocks and addresses of the transfer destination cell blocks, the specified data are combined automatically inside the memory. In detail, the aforementioned process corresponding to the transfer command is repeated for the number transfer source cell blocks.
REFERENCES:
patent: 4253059 (1981-02-01), Bell et al.
patent: 4779272 (1988-10-01), Kohda et al.
patent: 4870618 (1989-09-01), Iwashita
patent: 5-282883 (1993-10-01), None
patent: 7-235193 (1995-09-01), None
patent: 9-161491 (1997-06-01), None
Arent Fox Kintner Plotkin and Kahn PLLC
Fujitsu Limited
Tran Andrew Q.
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