Flash memory with coarse/fine gate step programming

Details Flash memory with coarse/fine gate step programming Flash memory with coarse/fine gate step programming

2006-06-06

2006-06-06

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185140, C365S185010

Reexamination Certificate

active

07057934

ABSTRACT:
A flash memory includes multi-level cells (MLC) that are programmed with a combination of coarse gate voltage steps and fine gate voltage steps. The multi-level cells include floating gate transistors that are programmed by modifying the threshold voltages of the floating gate transistors. Coarse gate voltage steps are used until the threshold voltage any of the transistors being programmed reaches a reference value, and fine steps are used thereafter.

REFERENCES:
patent: 6700820 (2004-03-01), Elmhurst et al.
patent: 6744670 (2004-06-01), Tamada et al.
patent: 6747893 (2004-06-01), Uribe
patent: 6894929 (2005-05-01), Matsuoka et al.
patent: 6937520 (2005-08-01), Ono et al.
patent: 6954446 (2005-10-01), Kuffner
patent: 2004/0156241 (2004-08-01), Mokhlesi et al.

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