Flash memory with accelerated transient state transitions

Details Flash memory with accelerated transient state transitions Flash memory with accelerated transient state transitions

2002-12-12

2003-09-30

Le, Thong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S201000, C365S210130

Reexamination Certificate

active

06628548

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to non-volatile memory, and more particularly, to a non-volatile memory that utilizes extra devices to accelerate transient state transitions, and disables extra load units to maintain the sensitivity of operating margins when reading data.
2. Description of the Prior Art
The growth of the so-called information age has led to the storage of mass quantities of information in digital form. Memory storage devices are thus an important topic of research and develop. Flash memory has become prevalent, allowing the access of data at speeds comparable to those of other forms of electronic memory, while storing digital data in a non-volatile manner without requiring any moving parts. Flash memory has thus become one of the most important types of non-volatile storage devices.
Please refer to
FIG. 1
, which is a circuit diagram of a prior art flash memory
10
. The flash memory
10
is biased by DC current V
dd
, and has a plurality of memory units
11
A and
11
B, two on-load isolating units
12
A and
12
B, a sensor unit SA
1
, two p-type MOS transistors Ta
1
and Ta
3
for load units, and a p-type MOS Ta
7
for reference units. In memory units
11
A and
11
B, MOS transistors Ma
1
and Ma
2
have floating gates to store data. The gates of MOS transistors Ma
1
, Ma
2
, TA
1
and TA
2
are controlled by the controlling voltage V
ma1
, V
ma2
, V
d1
and V
d2
respectively to determine whether the MOS is on or off. The MOS transistor TA
1
of the memory unit
11
A is also electrically connected to one end of the MOS transistor Ma
1
; the other end serves as a data end, and is electrically connected with on-load isolating at the node Na
5
. Similarly, an end of MOS transistor TA
2
of the memory
11
B is electrically connected with the node Na
5
, and serves as a data end of the memory unit
11
B. On-load isolating units
12
A and
12
B utilize inverters Iva
1
, Iva
2
and p-type MOS transistors Ta
5
, Ta
6
, respectively. The p-type MOS transistors serve as a loading unit, connecting to provide negative feedback, of which the source electrode is connected to the node Na
1
with the load unit
12
A, and the drain electrode is grounded. The source electrode of the MOS transistor Ta
3
, serving as a third end, connects with the on-load isolating unit
12
B at the node Na
3
, and its drain electrode is grounded. The sensor unit SA
1
is a differential sensing amplifier, comprising a first comparing end N
1
a and a second comparing end N
2
a, which are connected respectively to the nodes Na
1
and Na
3
; the sensor unit SA
1
compares the first comparing end N
1
a to the second comparing end N
2
a, and then generate a data signal V
rp1
. The MOS transistor Ta
7
with a floating gate electrode serves as a reference unit, of which its gate electrode is controlled by the controlling-voltage V
ca
; one of the other two electrodes is connected to the power V
dd
, and the other is connected to the node Na
6
with the on-load isolating unit
12
B.
The principle of operation for storing data into flash memory is to store each bit to one of the memory units that contains transistors with floating gates. Programming a bit into a memory unit, represented by a binary “0” or a binary “1” is performed by injecting differing amounts of electric charge. The floating-gate electrode is injected with a different amount of electric charge, which changes the threshold voltage. Even when under the same condition of voltage bias, the different amount of electric charge in the floating-gate results in a different conductance of the MOS transistor, and thus different amounts of data current. Accordingly, it is possible to read out the data stored in the floating-gates of all the memory units. As shown in the
FIG. 1
, when the memory
10
is to read the binary data stored in the memory unit
11
A, the memory
10
controls the controlling-voltage V
ma1
to bias and turn on the MOS transistor Ma
1
from the gate electrode, and the MOS transistor Ma
1
then generates a data current If
1
. The memory
10
also turns on the MOS transistor TA
1
by a high-voltage level V
d1
, so that the data current I
f1
can flow through the MOS transistor TA
1
via the node Na
5
. Of course, the MOS transistor TA
2
of the memory unit
11
B is turned off by the controlling-voltage V
d2
, which prevents the memory
11
B from outputting data current I
f1
to the node Na
5
, and thus prevents interfere when reading the data from the memory unit
11
A. The on-load insolating unit
12
A transmits data current I
f1
to the node Na
1
, and injects the current I
f1
into the MOS transistor Ta
1
, which is the load unit. With the MOS transistor Ta
1
current-biased by this data current I
f1
, the MOS transistor Ta
1
establishes a corresponding voltage at the node Na
1
. When the MOS transistor Ta
1
is turned on, the controlling-voltage V
ca
turns on the MOS transistor Ta
7
, which also serves as a reference unit, making the MOS transistor Ta
7
generate a reference current I
r1
, and injecting the current I
r1
into the MOS transistor Ta
3
. Serving as the load unit, after the MOS transistor Ta
3
is biased with this reference current I
r1
, the MOS transistor Ta
3
generates a corresponding voltage at the node Na
3
. The sensor unit SA
1
compares the voltage at Na
1
with the voltage at Na
3
through the first comparing end N
1
a and the second comparing end N
2
a, and generate a corresponding data signal V
rp1
, which reads out the data in the memory unit
11
A.
The process of reading data is further illustrated in FIG.
2
. Please refer to FIG.
2
and FIG.
3
.
FIG. 2
is a graph of voltage versus time at first comparing end N
1
a and the second comparing end N
2
a when the memory
10
is in process of reading data; the X-axis represents time, and the Y-axis represents the voltage; the curves V(N
1
a)H and V (N
1
a)L represent voltage at the first comparing end N
1
a varying with time, whereas the curve V(N
2
a) represents the voltage at the second comparing end N
2
a. Before the timing point ta
0
, the memory
10
has not yet read the data, and the first and the second comparing ends, N
1
a and N
2
a, are charged to high-voltage levels. When the time reaches ta
0
, the MOS transistors Ma
1
and Ta
7
generate current, and pull down the voltages of the first comparing end Na
1
and the second comparing end Na
2
. As mentioned above, differing amounts of electric charge stored in the floating gate of the MOS transistor Ma
1
in the memory unit
11
A results in a different data current I
f1
. When the data current I
f1
is greater (indicating a lower threshold voltage), the voltage of the first comparing end N
1
a will have the shape of V(N
1
a)H, and eventually falls to a higher steady-state voltage V
aH
; on the other hand, when the data current I
f2
is smaller, the voltage of the first comparing end N
1
a will follow curve V(N
1
a)L, and eventually falls to a lower steady-state voltage V
aL
. Similarly, the voltage of the second comparing end N
2
a falls to a steady-state voltage V
aR
. During the interval between ta
0
and ta
2
, the inverters Iva
1
and Iva
2
in the on-load isolating units
12
A and
12
B respectively and adequately bias the MOS transistors Ta
5
and Ta
6
, which lightens the load-effect occurring at the nodes Na
1
and Na
3
to accelerate the speed at which a steady-state is reached. When the voltages of the two comparing-ends N
1
a, N
2
a have reached their respective steady-state voltages, the sensor-unit SA
1
determines what data is stored in the memory
11
A by detecting the voltage difference between the two comparing ends N
1
a, n
2
a. When the voltage of the first comparing end N
1
a is greater than that of the second comparing end N
2
a, the electric charge stored in the MOS transistor Ma
1
corresponds to a greater data current. The sensor unit SA
1
thus decides if the data stored in the memory unit
11
A is a binary “0” or a binary “1”, and accordingly generates a data signal V
rp1
.
It's common to utilize many mem

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