Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-11-04
2000-01-18
Yoo, Do Hyun
Static information storage and retrieval
Floating gate
Particular biasing
365218, G11C 1300
Patent
active
060162759
ABSTRACT:
A wear leveling system and method of a flash memory cell uses the amount of time required to perform an erasing operation on a sector of the flash memory to determine whether the memory cells in the sector have degraded to an unacceptable level. The actual time required to erase a sector of a flash memory array is compared to a reference erasing time required to erase a unit sector under the state of the worst allowable degradation. If the actual erasing time of a sector exceeds the reference erasing time, logical addresses corresponding to the sector are re-mapped to the physical addresses of a different sector. On the other hand, when the actual erasing time is shorter than or equal to the reference erasing time, a controller continues to use the unit sector.
REFERENCES:
patent: 5341339 (1994-08-01), Wells
patent: 5568423 (1996-10-01), Jou et al.
patent: 5715193 (1998-02-01), Norman
patent: 5719808 (1998-02-01), Harari et al.
patent: 5805501 (1998-09-01), Shiau et al.
patent: 5809515 (1998-09-01), Kaki et al.
patent: 5912848 (1999-06-01), Bothwell
patent: 5917757 (1999-06-01), Lee et al.
patent: 5920501 (1999-07-01), Norman
LG Semicon Co. Ltd.
Yoo Do Hyun
LandOfFree
Flash memory wear leveling system and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flash memory wear leveling system and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory wear leveling system and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-567385