Flash memory VDS compensation techiques to reduce programming va

Details Flash memory VDS compensation techiques to reduce programming va Flash memory VDS compensation techiques to reduce programming va

1997-03-31

1998-08-25

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518526, 36518529, 36518533, 365218, G11C 1134

Patent

active

057989664

ABSTRACT:
A nonvolatile memory device. For one embodiment, the nonvolatile memory device includes a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate. The nonvolatile memory device also includes a source voltage generator circuit coupled to the source line and generating a source line voltage when programming the nonvolatile memory cell. The source voltage generator circuit varies the source line voltage based on a location of the nonvolatile memory cell in the memory array. The nonvolatile memory device may also include a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming the nonvolatile memory cell. The drain voltage generator circuit varies the bit line voltage based on the location of the nonvolatile memory cell in the memory array.

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