Flash memory test system

Details Flash memory test system Flash memory test system

1997-10-15

1999-04-20

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058963987

ABSTRACT:
A flash memory test system supplies test data to a flash memory under test to write the test data in the specified address of the memory and compares the data in the specified address with expected data to determined whether the data writing for the address is completed. If the data writing is unsuccessful, the write operation is repeated until the test data is correctly stored in the address or the predetermined maximum number of the write operation is reached. The number of repeated write operation is recorded for each address and displayed relative to the physical image of the flash memory under test. The flash memory test system includes a comparator for comparing the data in the flash memory under test with the expected data, a fail counter for counting the number of write operation, a fail analysis memory for storing fail information and the counted numbers, and a work station for processing the fail information and the counted numbers and displaying the results of the analysis with respect to a physical image of the flash memory under test.

REFERENCES:
patent: 5793774 (1998-08-01), Usui et al.

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