Flash memory system having reduced disturb and method

Details Flash memory system having reduced disturb and method Flash memory system having reduced disturb and method

1995-08-01

1997-04-01

Nelms, David C.

Static information storage and retrieval

Floating gate

Disturbance control

36518533, 3652335, G11C 1134

Patent

active

056173504

ABSTRACT:
A flash memory system having a reduced tendency to have its erased cells disturbed during read operations. An array of flash memory cells are arranged into a multiplicity of rows and columns, with all of the cells located in one of array rows has a control gate connected to a common word line and with all of the cells in a column has a drain connected to a common bit line. Control circuitry is used for carrying out memory operations, including program circuitry for programming cells of the array based upon a program input address and read circuitry for reading cells of the array based upon a read input address. The read means functions to apply a read voltage to a selected one of the word lines of the array as determined by the read input address. Disturb limit circuitry is used for limiting the time period that the read circuitry applies the read voltage to the selected one of the word lines.

REFERENCES:
patent: 5317535 (1994-05-01), Talreja et al.
patent: 5434815 (1995-07-01), Smarandoiu et al.

Affiliated with

Also associated with

Rating

Flash memory system having reduced disturb and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flash memory system having reduced disturb and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory system having reduced disturb and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-544933