Flash memory system having cross-coupling compensation...

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185230, C365S185200

Reexamination Certificate

active

07990767

ABSTRACT:
A method for reading an addressed cell of a memory system comprises applying at least two different voltage levels to a control gate of a memory cell in an array of memory cells, wherein the memory cell is adjacent to and in electrical field communication with the addressed memory cell. A threshold voltage of the addressed memory cell is measured at each of the at least two different applied voltage levels. At least two of the measured threshold voltages of the addressed memory cell are converted to one or more bit values stored in the addressed memory cell. The bit values are provided to a host of the memory system. An apparatus implementing the method is also disclosed.

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International Search Report issued in international application No. PCT/IB2010/003338, mailed May 3, 2011 (5 pages).
International Written Opinion issued in international application No. PCT/IB2010/003338, mailed on May 3, 2011 (8 pages).

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