Static information storage and retrieval – Addressing – Byte or page addressing
Reexamination Certificate
2002-09-25
2004-04-27
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Byte or page addressing
C365S185330, C365S185080
Reexamination Certificate
active
06728164
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of priority from prior Japanese Patent Application P2001-294204 filed on Sep. 26, 2001; the contents of which are incorporated by reference herein.
FIELD OF THE RELATED ART
The present invention relates to a method for rewriting information of a memory IC card, and more particularly relates to a flash memory rewrite circuit which is used in the case of rewriting information data using a flash memory IC card, a semiconductor integrated circuit for an memory IC card, a memory IC card, a flash memory rewriting method, and a flash memory rewriting program.
BACKGROUND
FIG. 1
illustrates the structure of a large scale integrated device (LSI)
41
for an integrated circuit card (IC card) for general use. Though flash memory
14
, serving as memory on LSI
41
, is illustrated, an EEPROM and the like may be used in place of the flash memory
14
as illustrated in FIG.
2
. First, an explanation will be given of a rewriting method in a case where an EEPROM
17
is used as memory of
FIG. 2. A
CPU
11
designates data and an address for a designated byte for rewriting in EEPROM
17
via a bus
10
. Since the designated byte for rewriting data is directly designated by the CPU
11
, data can be rewritten for each designated byte. However, since EEPROM
17
increases an area, EEPROM
17
cannot respond to the need for an increase in capacity in such a system that has a determined maximum chip area such as an IC card. Accordingly, EEPROM
17
is often used in an IC card of up to about 16 Kbytes. On the other hand, the LSI
41
using flash memory
14
as shown in
FIG. 1
can respond to the need of an IC card up to about 128 Kbytes. However, since the flash memory
14
generally performs rewriting per block, an operation must be carried out according to a special flow in order to perform rewriting for each designated byte.
The rewriting method of flash memory
14
will be explained using a flowchart of FIG.
3
and
FIG. 4
with reference to
FIG. 1
(a) In step S
301
of
FIG. 3
, page P
m
including designated byte b
k
for rewriting data in flash memory
14
is stored in RAM
12
from flash memory
14
via bus
10
according to an instruction from CPU
11
. One page refers to a page that uses 64 bytes as one unit (block). In the flash memory, rewriting is generally carried out per block (page) in this way.
(b) Next, in step S
302
, data for designated byte b
k
for rewriting data is written over page data for page P
m
stored in RAM
12
via bus
10
according to an instruction from CPU
11
. This overwritten new page data for page P
m
is data to be newly written to flash memory
14
.
(c) Next, in step S
303
, new page data for page P
m
prepared in the RAM
12
is set at a page address of flash memory
14
via bus
10
according to an instruction from CPU
11
.
(d) Next, in step S
304
, page data for page P
m
of the flash memory
14
is rewritten according to an instruction from CPU
11
.
Problem arises in the EEPROM, because data and an address for a designated byte for rewriting are directly designated, so that rewriting can be carried out in one step. On the other hand the byte rewriting of flash memory needs the plurality of steps as discussed above. For this reason, program developers must create an application with consideration given to the way of handling data for all bytes corresponding to one page including rewriting portions even when designated data with several bytes are stored.
Furthermore especially, in the EEPROM, rewriting per byte can be carried out in one step but the capacity is small, while the flash memory can deal with the large capacity but needs several steps to perform rewriting per byte.
SUMMARY
According to an aspect of the present invention, a flash memory rewrite circuit including: a rewrite data control circuit, receiving a rewrite instruction of a flash memory from a CPU to store data for a designated byte of a page for rewriting to a memory block; a wait control circuit, generating and canceling a wait instruction to the CPU; a page data control circuit, sending data of the page excluding the designated byte to the memory block from the flash memory to prepare new page data in the memory block; and a data set control circuit that writes the new page data prepared in the memory block into the flash memory.
According to another aspect of the present invention, a flash memory rewriting method including: receiving a rewrite instruction of a flash memory from a CPU; storing data for a designated byte of a page for rewriting to a memory block; generating a wait instruction to said CPU; sending data of said page excluding the designated byte to said memory block from said flash memory to prepare new page data in said memory block; setting said new page data prepared in said memory block at an page address of said flash memory; rewriting data of said flash memory; and canceling said wait instruction to said CPU.
The features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5677843 (1997-10-01), Mizuno et al.
patent: 5748537 (1998-05-01), Garbers et al.
patent: 5847997 (1998-12-01), Harada et al.
patent: 6005810 (1999-12-01), Wu
patent: 2000-339212 (2000-12-01), None
patent: 2001-60167 (2001-03-01), None
Elms Richard
Hur J. H.
Kabushiki Kaisha Toshiba
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