Flash memory programming and verification with reduced...

Details Flash memory programming and verification with reduced... Flash memory programming and verification with reduced...

2006-04-05

2009-12-08

Mai, Son L (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185160, C365S185180

Reexamination Certificate

active

07630253

ABSTRACT:
A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

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PCT Search Report for PCT/US07/08606, Sep. 18, 2007, Spansion LLC.
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