Flash memory including means of checking memory cell...

Details Flash memory including means of checking memory cell... Flash memory including means of checking memory cell...

2001-11-15

2003-05-27

Nelms, David (Department: 2818)

Motors: spring, weight, or animal powered

Animal powered

Belt tread

C185S016000, C185S016000, C185S016000

Reexamination Certificate

active

06568510

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to electrically erasable and programmable memories, and more particularly, to a flash memory that is erasable by page.
BACKGROUND OF THE INVENTION
The market for electrically erasable and programmable integrated circuits comprises essentially EEPROM memories and FLASH (or FLASH-EEPROM) memories. EEPROM memories may be of the programmable type erasable by word or the programmable type erasable by page. Due to the current technology, FLASH (or FLASH-EEPROM) memories are usually programmable by a word and erasable by a sector. A sector usually contains a large number of pages.
FIG. 1
diagrammatically shows a FLASH memory array including a plurality of memory cells CF
i,j
laid out in matrix fashion and connected to word lines WL
i
and bit lines BL
j
. The memory cells CF
i,j
in the FLASH memory have a very straightforward structure and comprise only a floating gate transistor FGT. In this case an NMOS transistor with its gate G connected to a word line WL
i
, its drain D connected to a bit line BL
j
and its source S connected to a source line SL
i
. The bit lines BL
j
are grouped in columns of rank k to form binary words W
i,k
, for example, each including eight cells VF
i,j
(bytes). The cells in a particular word W
i,k
may be adjacent (as shown in
FIG. 1
) or they may be interlaced with cells belonging to other words. A physical page Pi in the FLASH memory is formed by the set of memory cells C
i,j
connected to the same word line WL
i
, and thus comprises a plurality of binary words W
i,k
. A sector is formed by a set of pages P
i
, in which the source lines SL
i
are interconnected and are always at the same electrical potential.
In this type of FLASH memory, programming of a cell includes injecting electrical charges into the floating gate by a “hot electron injection” effect, while erasing a cell includes extracting electrical charges trapped in the floating gate by the tunnel effect. An erased FGT transistor has a positive threshold voltage VT
1
with a low value, and a programmed transistor has a threshold voltage VT
2
greater than VT
1
. When a read voltage V
READ
between VT
1
and VT
2
is applied to its gate, an erased transistor will be conducting, which by convention corresponds to reading a logical 1. A programmed transistor will remain blocked, which by convention corresponds to reading a logical 0.
Due to the simplicity of their memory cells which do not include any access transistors as in EEPROM memories, FLASH memories have the advantage of being very compact in terms of the area of occupied silicon and thus, for the same silicon area, have a significantly greater storage capacity than EEPROM memories at a lower cost. On the other hand, they are less flexible in use due to the need to simultaneously erase all memory cells in the same sector.
However, some applications benefit from the advantages of FLASH memories (compactness and low cost) while benefiting from the possibility of erasing by page, for example, when the volume of data to be recorded is small and it would be impossible to erase an entire sector before programming a page. However, there are some difficulties for a FLASH memory erasable by page.
To understand the problem that arises, it is important to first remember that a memory cell can be erased using the source erase method, or the channel erase method.
The source erase method shown in
FIG. 1
includes applying a positive erasing voltage V
ER+
on the order of 4 to 5 V to all source lines SL
i
in the same sector, while the word lines WL
i
in the sector considered receive a negative erase voltage V
ER−
on the order of −8V. The material forming the transistor channel (substrate or well) is grounded. The voltage difference that exists between the source S and the gate G of the transistors has the effect of tearing off electrical charge trapped in the floating gates (by the tunnel effect) and erasing the transistors. The negative voltage V
ER−
is applied to the gates of all transistors in the same sector by inhibiting a word line decoder XDEC (FIG.
1
). The voltage V
ER−
is applied to the input of this decoder, and the decoder then applies this voltage to all word lines WL
i
in the sector to be erased regardless of the address received at the input. At the same time, the impedance of all outputs from a column decoder YDEC connected to bit lines BL
j
is set to a high level.
Channel erasing is different from source erasing in that the positive erasing voltage V
ER+
is applied to the transistor sources through the material forming the channel regions (substrate or well) to which a biasing voltage VB is applied. The PN junctions that exist between the channel regions and the source regions are biased to make them conducting, and the voltage V
B
is applied to all transistor sources in the same sector to form the voltage V
ER+
. At the same time, the negative erase voltage V
ER−
, as before, is applied to the gates of transistors through the word line decoder XDEC that is in the inhibited state.
The advantage of channel erasing is that the channel regions and source regions are at approximately the same electrical potential, since channel/source junction diodes ate biased to make them conducting. Therefore, compared with source erasing, there is no more leakage current in the source/channel direction. The erase voltage V
ER+
may be increased to a higher potential than in the case of source erasing, for example, 8 to 10V compared with 4 to 5V in the first case.
One known approach for making a FLASH memory erasable by page includes providing a selection transistor for each source line SL
i
capable of a selectively applying the programming voltage V
ER+
. This type of approach is in line with the information disclosed in patent EP 704,851 and application WO 98/33187, in which a word is selectively erased by equipping cells of a single word with a source selection transistor.
However, this approach has a number of disadvantages. First, a FLASH memory cell is programmed with a non-negligible drain-source current. Consequently, if all cells in a word are programmed simultaneously, a high current is collected by the source line selection transistor. This current increases the drain-source voltage of the selection transistor, and there is a corresponding reduction in the drain-source voltage of the floating gate transistors, and an increase in the programming time. Therefore, the cells in a same word must be programmed individually, or at the same time as cells belonging to other binary words (WO 98/33187).
Furthermore, the use of source line selection transistors is not compatible with the channel erase method. The erase voltage V
ER−
in this case is applied through the material forming the channel. Consequently, the use of source line selection transistors does not prevent the voltage V
ER−
from reaching the transistor sources and creating an electrical field causing tearing off of charge trapped in the floating gates.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the present invention is to provide a process for selective erasure of a page in a FLASH memory sector that does not require the use of source line selection transistors.
Another object of the invention is to provide a process for selective erasure of a page in a FLASH memory sector that is compatible with the channel erase method.
Another problem that this invention is intended to solve relates to “refreshment” of the memory cells of a FLASH memory. In other words, reprogramming of cells in which the threshold voltage is modified. The provision of a FLASH memory erasable by page is only useful if the user is allowed to erase and reprogram the same page a large number of times without worrying about other memory pages. However, the memory cells of the other pages are directly connected to the bit lines BL
i
and are not protected by an access transistor as in the case of EEPROM memories. The memory cells will repeatedly receive on their

Affiliated with

Also associated with

Rating

Flash memory including means of checking memory cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flash memory including means of checking memory cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory including means of checking memory cell... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3036665