Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2008-02-27
2010-02-23
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185020, C365S210130, C365S042000, C365S042000
Reexamination Certificate
active
07668010
ABSTRACT:
A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.
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Chen Ming Shang
Han Tzung Ting
Ku Shaw Hung
Lee Shih Chin
Lin Shang Wei
Haynes Beffel & Wolfeld LLP
Macronix International Co. Ltd.
Nguyen Tan T.
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