Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-10-07
1997-12-16
Nguyen, Tan T.
Static information storage and retrieval
Floating gate
Particular biasing
36518522, 36518524, 36518533, G11C 1600
Patent
active
056992980
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to floating gate memory devices, such as flash memory, and in particular to methods and circuits for erasing arrays of floating gate memory cells with reduced peak current consumption.
2. Description of Related Art
Non-volatile memory based on integrated circuit technology represents an expanding field. Several popular classes of non-volatile memory are based on arrays of floating gate memory transistors which are electrically erasable and programmable.
The act of programming a memory array of floating gate memory transistors in one common approach involves injecting the floating gates of addressed cells with electrons, which causes a negative charge to accumulate in the floating gate and the turn-on threshold of the memory cell to increase to a high threshold state. Thus, when programmed, the cells will not turn on, that is, they will remain non-conductive, when addressed with read potentials applied to the control gates. The act of erasing a cell having a negatively charged floating gate involves removing electrons from the floating gate to lower the threshold. With the lower threshold, the cell will turn on to a conductive state when addressed with a read potential to the control gate. For an opposite polarity array, programming involves selectively removing electrons from the addressed cells' floating gates.
During the erase process in flash memory devices, an erasing potential is applied in parallel to the entire array, or to large sectors of the array. Thus, the power supply used during the erasing procedure must be capable of handling the current required for the erase process in large number of cells in parallel. The primary current in the erase process is so called Fowler-Nordheim (F-N) tunneling current by which electrons are driven from the floating gate into the source of the floating gate memory cell. Another source of current during the erasing procedure is known as band-to-band tunneling. Band-to-band tunneling results in current into the substrate, and current in the form of unwanted holes injected in the direction of the floating gate. Most of these unwanted holes stay in an area about 15-30 Angstroms away from the surface of the silicon. Because threshold voltage of the cell is based on the sum of the charges at the floating gate (electrons for example), and the charges in the area between the floating gate and the silicon surface (trapped holes, for example), and these holes can easily de-trap and change the sum of charge, the reliability of the cells is reduced. See, for example, Ajika et al., "A Five Volt Only 16M Bit Flash EEPROM Cell With a Simple Stacked Gate Structure", IEDM 1990, page 115-118; and Wann, et al., "Suppressing Flash EEPROM Erase Leakage with Negative Gate Bias and LDD Erase Junction", Symposium on VLSI Technology 1993, pages 81-82. As described in Wann, et al., use of a negative gate potential during the erase process, allows use of a lower source voltage. The lower source voltage suppresses avalanche breakdown and improves endurance and reliability of the cell. However, unwanted band-to band tunneling current is not reduced for a given erase speed in Wann, et al. According to Wann, et al., to further suppress the band-to-band tunneling, erase speed is sacrificed.
Band-to-band tunneling current is related to the threshold of the cell being erased. Thus, a problem arises in flash memory devices, because cells in the high threshold state do not all have the same threshold. Therefore, many cells in the high threshold state will have a higher threshold level than others. For example, some cells may have a threshold of 8 volts, while others may have a threshold of 6 volts. The band-to-band tunneling current generated in the higher threshold cells (e.g. near 8 volts) is greater than that in the lower threshold cells (e.g. near 6 volts). Therefore, higher threshold cells create significant band-to-band tunneling current during an erase process. Because the flash erase procedure involves erasing a
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Chen Han Sung
Chuang Weitong
Hung Chun-Hsiung
Liu Yuan-Chang
Shiau Tzeng-Huei
Macronix International Co. Ltd.
Nguyen Tan T.
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