Flash memory device with reduced erase time

Details Flash memory device with reduced erase time Flash memory device with reduced erase time

2008-05-13

2008-05-13

Dinh, Son (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290

Reexamination Certificate

active

11405577

ABSTRACT:
A NOR flash memory device comprises a memory cell array, a row selection circuit adapted to drive wordlines in the memory cell array with a wordline voltage during an erase operation, and an erase voltage generating circuit adapted to generate an erase voltage as the wordline voltage during the erase operation. The erase voltage generating circuit includes a discharging circuit receiving a high voltage that is regularly maintained irrespective of variations in a power voltage, and discharging the erase voltage supplied from the wordline during an erasing recovery period of the erase operation.

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