Flash memory device with NAND architecture with reduced...

Details Flash memory device with NAND architecture with reduced... Flash memory device with NAND architecture with reduced...

2008-07-01

2008-07-01

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180

Reexamination Certificate

active

07394694

ABSTRACT:
A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.

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Seungjae Lee et al., “A 3.3V 4Gb Four-Level NAND Flash memory with 90nm CMOS Technology,” 2004 IEEE International Solid-State Circuits Conference, Session 2, Non-Volatile Memory, 2.7.

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