Flash memory device with multiple erase voltage levels

Details Flash memory device with multiple erase voltage levels Flash memory device with multiple erase voltage levels

2007-09-11

2007-09-11

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185330, C365S185290, C365S185120, C365S185110, C365S185170

Reexamination Certificate

active

11383157

ABSTRACT:
In some embodiments, a string of nonvolatile memory cells may be erased by driving their control gates with erase voltages that may have different levels for different cells. The cells may be divided into two or more groups, and the cells in each group may be driven by the same erase voltage. In another embodiment, a nonvolatile memory device may include a cell array having two groups of memory cells, and the memory cells in different groups may be simultaneously driven with erase voltages having different levels during an erase operation.

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English language abstract of Japanese Publication No. 2000-348493.
English language abstract of Japanese Publication No. 2003-051193.
English language abstract of Japanese Publication No. 2005-032368.

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