Flash memory device with multiple checkpoint erase suspend logic

Details Flash memory device with multiple checkpoint erase suspend logic Flash memory device with multiple checkpoint erase suspend logic

1996-10-03

1998-09-08

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518533, 365218, 395430, G11C 1604

Patent

active

058055010

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to the field of nonvolatile semiconductor memories, and more particularly to processes for suspending an automated erase sequence of a flash memory device.
2. Description of Related Art
A flash memory device is based on a memory array of floating gate transistors which are organized into a plurality of blocks of memory cells in many current architectures, in order to support block by block programming and erasing of the array of cells. See U.S. Pat. No. 5,414,664; entitled FLASH EPROM WITH BLOCK ERASE FLAGS FOR OVER-ERASE PROTECTION; invented by Lin, et al. For a typical flash memory cell, a logic "1" corresponds to an erased state, in which fewer electrons are stored in the floating gate of the cell, and therefore the erased cell has a low threshold. When a read voltage is applied to the control gate of the cell which has been erased, then the cell is conductive. On the other hand, a logic "0" corresponds to a programmed state, in which the floating gate has more electrons stored in it. In the programmed state, the cell has a high threshold, such that upon application of a read potential to the word line, the cell is not conductive. (Of course, the logic values of the programmed and erased states can be assigned however best suits a given implementation). Flash memory cells are characterized by the fact that a single memory cell cannot be over written from the logic 0 or programmed state to the logic 1 or erased state, on a bit-by-bit basis. Thus, in order to set a cell to a desired state, the entire block must be erased first, and then those cells which are intended to have the logic 0 stored in them, are individually programmed.
The erase procedure is typically automatically controlled by an internal state machine on the device. This procedure takes relatively a long time. For example, prior art erase procedures consist of a number of steps including pre-programming and verifying the pre-programming of all the bytes in the block, and erasing the entire block followed by verification of the erase of all the bytes in the block.
It may happen that during an erase procedure, a user will desire to read data stored in blocks other than the one that is being erased. In order to accomplish a read, it is desirable to suspend the ongoing erase procedure, allow the read access to proceed, and then resume the erase procedure after the read access is complete.
One prior art erase suspend process is described in prior art U.S. Pat. No. 5,355,464; entitled CIRCUITRY AND METHOD FOR SUSPENDING THE AUTOMATED ERASURE OF A NON-VOLATILE SEMICONDUCTOR MEMORY; invented by Fandrich, et al. As described in the Fandrich, et al. patent, the erase suspend command may be issued by the user at any time. However, the erase procedure according to Fandrich, et al. can only be suspended at certain places in the erase procedure (See, FIG. 5 of Fandrich, et al). For example, during the preconditioning phase of the erase procedure (during which pre-programming is done), the state machine responds to the erase suspend command only after successful pre-programming of a current byte being pre-programmed. To pre-program a byte, a program pulse is applied to the byte, and then a verification test is executed. If the verify fails, then another program pulse is applied and the verification is retried. This pulse and verify loop can continue for a number of cycles until the byte is successfully programmed, or the algorithm fails. By requiring a user to wait until a successful pre-programming has been accomplished for the current byte subject of the pre-programming procedure, significant delays are encountered by the user in attempting to make an access to another block in the array during the erase process.
In Fandrich, et al., a second point at which the erase procedure responds to a suspend command is during the erase phase of the process. In Fandrich, et al., the erase phase involves a relatively long erase pulse (on the order of milliseconds) which is applied.

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