Flash memory device with multi level cell and burst access...

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185180, C365S185220

Reexamination Certificate

active

08045376

ABSTRACT:
A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

REFERENCES:
patent: 6097635 (2000-08-01), Chang
patent: 6324115 (2001-11-01), Choi
patent: 6385110 (2002-05-01), Deguchi
patent: 6427025 (2002-07-01), Shimomura et al.
patent: 6483743 (2002-11-01), Talreja
patent: 2003/0002334 (2003-01-01), Ho Chang
patent: 2008/0177934 (2008-07-01), Yu et al.
patent: 08-315586 (1996-11-01), None
patent: 10-233096 (1998-09-01), None
patent: 2005-7653 (2001-01-01), None

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