Flash memory device having multi-level cell and reading and...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185190, C365S185220, C365S185240, C365S185230, C365S185140, C365S185030

Reexamination Certificate

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07035144

ABSTRACT:
There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.

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patent: 6243290 (2001-06-01), Kurata et al.
patent: 6363010 (2002-03-01), Tanaka et al.
patent: 6807096 (2004-10-01), Toda
patent: 6937510 (2005-08-01), Hosono et al.
patent: 2003/0137888 (2003-07-01), Chen et al.
patent: 2004/0057310 (2004-03-01), Hosono et al.
patent: 2004/0125651 (2004-07-01), Toda

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