Flash memory device having a multi-bank structure

Details Flash memory device having a multi-bank structure Flash memory device having a multi-bank structure

2001-12-27

2002-12-24

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189090, C365S210130

Reexamination Certificate

active

06498764

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a flash memory device of a multi-bank structure, and more particularly to, a flash memory device of a multi-bank structure capable of allowing a dual operation without increasing the area of the multi-bank structure of more than 2-bank, by discriminating a read address and a write address depending respective operations and determining the banks depending on the bank address allocated in an input address.
2. Description of the Prior Art
In order to implement higher-speed and higher-integration semiconductor memory devices, a plurality of memory cell arrays are constituted in a plurality of blocks and the plurality of blocks are arranged in a row and column direction to form a single bank. Generally, a single bank includes a memory cell array, a raw and column decoder and a pass gate.
FIG. 1
is a block diagram showing a conventional 2-bank flash memory device far implementing a dual operation. The structure and operation of the 2-bank flash memory device will be below explained.
An address latch means
102
that receives an address ADDR buffered in an address buffer
101
, outputs a first bank address BANK
1
ADDR and a second bank address BANK
2
ADDR. A first bank row decoder
103
and a first bank column decoder
104
both constituting a first bank
10
selects a first bank memory cell array
107
and a first pass gate
108
depending on the first bank address BANK
1
ADDR from the address latch means
102
to select a given cell of the first bank memory cell array
107
. Meanwhile, a second bank row decoder
105
and a first bank column decoder
106
both constituting a second bank
20
selects a second bank memory cell array
110
and a second pass gate
111
depending on the second bank address BANK
2
ADDR from the address latch means
102
to select a given cell of the second bank memory cell array
110
. A first sense amplifier
109
senses the selected cell of the first bank memory cell array
107
to output its result, and a second sense amplifier
112
senses the selected cell of the second bank memory cell array
110
to output its result. The output results of the first and second sense amplifiers
109
and
112
, are outputted outside through a data latch means
113
and an input/output buffer
114
.
As above, the reason that the first and second bank addresses BANK
1
ADDR and BANK
2
ADDR are divided is to implement a dual operation far allowing the first bank
10
and the second bank
20
to perform separate operations. In other words, that is because an address for discriminating that the second bank
20
performs a read operation while the first bank
10
performs a write operation is necessary.
Therefore, in order to implement a dual operation in a multi-bank of more than 2-bank constructed above, an address bus line is increased by the number of the bank since the number of address is required as much as the number of the bank. For example, assuming that the number of address is twenties (20), forties (40) number of address bus lines is required in the 2-bank but if it is 4-bank, eighties (80) number of address bus lines are required.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problem and an object of the present invention is therefore to provide a flash memory device of a multi-bank structure capable of improving .the performance of devices by effectively constructing a dual operation without increasing the area of the multi-bank of more than 2-bank.
Another object of the preset invention is to a multi-bank semiconductor memory device for allowing a dual operation, by discriminating a read address and a write address depending respective operations and determining the banks depending on the bank address allocated in an input address.
In order to accomplish the above object, a semiconductor memory device of a multi-bank structure according to the present invention is characterized in that it comprises a plurality of banks having a memory cell array and a row and column decoder; a means for classifying an input address into a read address and a write address depending on read or write operation; a first selecting means for enabling one of the plurality of the banks depending on the bank address allocated to the input address and the read address to perform the read operation; a second selecting means for enabling one of the plurality of the banks depending on the bank address allocated to the input address and the write address to perform the write operation; a sense amplifier for sensing data of the bank to compare them with data of a reference cell; and a pumping means for supplying a given bias to the bank.
Also, the semiconductor memory device of a multi-bank structure further includes a first switching means connected between the plurality of the banks and the sense amplifier and driven depending on a control signal of the first selecting means.


REFERENCES:
patent: 6157580 (2000-12-01), Kohno
patent: 6160750 (2000-12-01), Shieh
patent: 6240040 (2001-05-01), Akaogi et al.
patent: 6327181 (2001-12-01), Akaogi et al.

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