Flash memory device capable of preventing program...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185020, C365S185110, C365S185280

Reexamination Certificate

active

10819385

ABSTRACT:
A non-volatile semiconductor memory device disclosed herein includes arrays of memory cells arranged along rows and columns. The columns are divided into at least two column regions and each row is divided into two electrically isolated word lines that are arranged in the column regions. The memory device further includes a determining circuit for judging which column region a data loaded on a register belongs to during a program operation, and a selecting circuit for choosing one of the rows in response to the row address information and driving one or all of the word lines in the selected row with a program voltage according to the judging.

REFERENCES:
patent: 5677873 (1997-10-01), Choi et al.
patent: 5815435 (1998-09-01), Van Tran
patent: 5991202 (1999-11-01), Derhacobian et al.
patent: 6081450 (2000-06-01), Nawaki
patent: 6542406 (2003-04-01), Byeon et al.
patent: 6731540 (2004-05-01), Lee et al.

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