Flash memory device and method that operates a memory cell array

Static information storage and retrieval – Floating gate – Particular connection

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Details

36518513, 36518523, 36518533, G11C 1604, G11C 1606

Patent

active

059462329

ABSTRACT:
A semiconductor device and method is providing having a memory cell array divided into a plurality of sectors and an erasing operation is preferably performed by sectors. The sectors are sub-divided into two or more sub-sectors, and at least one word line inside each of the sub-sectors is commonly coupled to another word line inside a different sub-sector. Thus, a plurality of word lines can be commonly coupled to a single word line decoder. Accordingly, a number of required word line decoders for the semiconductor device is reduced. Further, size and power requirements of the semiconductor device can be reduced.

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