Flash memory device and method for controlling erase...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185280, C365S189090

Reexamination Certificate

active

11594356

ABSTRACT:
A non-volatile memory device includes first and second memory cell blocks, each including a plurality of memory cells and including a local drain select line, a local source select line, and local word lines. A block selection unit connects given local word lines to global word line, respectively, in response to a block selection signal. A first bias voltage generator is configured to apply at least first and second erase voltages to the global word lines during an erase operation, the first erase voltage being applied to the global word lines during a first erase attempt of the erase operation, the second erase voltage being applied to the global word lines during a second erase attempt, where the second erase attempt is performed if the first erase attempt did not successfully perform the erase operation. The first and second erase voltages being positive voltages. A bulk voltage generator applies a bulk voltage to a bulk of the memory cells during the erase operation.

REFERENCES:
patent: 5818758 (1998-10-01), Wojciechowski
patent: 5991198 (1999-11-01), Song et al.
patent: 6327194 (2001-12-01), Kurihara et al.
patent: 6335882 (2002-01-01), Saeki et al.
patent: 7200039 (2007-04-01), Lee
patent: 2006/0044877 (2006-03-01), Kato
patent: 2006/0268653 (2006-11-01), Umezawa

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