Flash memory device

Static information storage and retrieval – Floating gate – Particular connection

Patent

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Details

365200, G11C 1606

Patent

active

058354077

ABSTRACT:
A flash memory device according to this invention comprises a main cell array block consisted of a main cell array and a dummy cell array; a first and second multiplex blocks to which data of the main cell array are input; a first and second column multiplex blocks to which data of the main cell array block are input; a first and second repair multiplexers to control the first and second multiplex blocks; a third to fifth repair multiplexers to control the first and second column multiplex blocks; a first to fifth decoders to access said main cell array of the cell array block according to an address input; a sixth and seventh decoders to access repair cell array of the cell array block according to the address input; and a redundancy fuse block comparing the inputted address with repair address and determining whether repair be done or not.

REFERENCES:
patent: 5471426 (1995-11-01), McClure
patent: 5485425 (1996-01-01), Iwai et al.
patent: 5696723 (1997-12-01), Tukahara
patent: 5737269 (1998-04-01), Fujita

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