Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2002-11-04
2004-07-13
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230010, C365S203000, C365S204000, C365S189090
Reexamination Certificate
active
06762970
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a flash memory device. More particularly, the invention relates to a flash memory device capable of improving lowering in the read-out speed due to loading of a word line, in such as way that a pumping circuit is driven by a standby mode, a read-out mode, and an enable signal that is generated when the power supply voltage is set up, and a capacitor having a large capacitance is charged by an output voltage from the pumping circuit to apply a voltage depending on an electric charge stored at the capacitor in the read-out mode to a word line driver and a bit line driver.
2. Description of the Prior Art
In order to read out a given cell of the flash memory device, it is required that a voltage of more than a given amount be applied to a word line of the cell. In order to read out a cell of the flash memory device operating at the power supply voltage of 1.8 V that has been currently developed, it is required that a voltage of 4 V be applied.
Referring to
FIG. 1
, a construction of a flash memory device using a boosting circuit for reading out a conventional flash memory cell will be described.
A boosting circuit
11
is driven by an address transfer detection signal ATD and outputs a boosting voltage higher than the power supply voltage. A word line decoder
12
decodes an address signal to select a word line of a given cell from a flash memory cell array
16
. A word line driver
13
applies the boosting voltage from the boosting circuit
11
to the word line of the cell selected by the decoding signal of the word line decoder
12
. Meanwhile, the bit line driver
14
drives a given bit line of the flash memory cell array
16
depending on an external voltage. The bit line decoder
15
decodes the address signal to select a given bit line of the flash memory cell array
16
.
In the conventional flash memory device constructed above, if the address signal add is shifted, the address transfer detection circuit detects the address signal add to output the address transfer detection signal ATD, as shown in FIG.
2
. The boosting circuit
11
is then driven by the address transfer detection signal ATD to output the boosting voltage higher than the power supply voltage. Also, the boosting voltage is supplied to the word line of the cell that is selected through the word line driver
13
. The word line is thus activated. As loading from the boosting circuit
11
to the word line is significantly large, however, it is required that the size of the pumping capacitor of the boosting circuit
11
be significantly large. Therefore, lots of time is consumed to boost the pumping capacitor up to a desired voltage. As such, as the word line is activated after a significant time delay since the address transfer detection signal ATD is outputted, there is a problem that the read-out speed is delayed.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide a flash memory device in which a word line is activated with no time delay, thus improving a read-out speed.
Another object of the present invention is to provide a flash memory device in which a word line is not boosted in a read-out mode and a boosting voltage is generated in a standby mode and a read-out mode, thus improving the read-out speed.
In order to accomplish the above object, a flash memory device according to the present invention, is characterized in that it comprises a pumping circuit for generating a pumping voltage higher than the power supply voltage depending on an enable signal generated when a standby mode, a read-out mode and a power supply voltage are set up, a capacitor for charging the potential depending on the pumping voltage of the pumping circuit, a word line decoder and a bit line decoder for decoding an address signal to select a word line and a bit line of a given cell from the flash memory cell array, and a word line driver and a bit line driver for applying a given voltage depending on an electric charge stored at the capacitor to the word line and the bit line of the selected cell in the flash memory cell array so that a read-out operation is performed.
Meanwhile, the pumping circuit comprises an oscillator driven by the enable signal, for outputting a signal of a period that is varied by the pumping voltage, a positive charge pump circuit for performing a pumping operation depending on the enable signal and the output signal of the oscillator to output the pumping voltage of a voltage higher than the power supply voltage, a dividing means for dividing the pumping voltage of the positive charge pump circuit, an edge trigger for sensing a rising edge of the output signal in the oscillator to output a signal delayed by a given time, a reference voltage generator for generating a reference voltage depending on the output signal of the edge trigger, a differential amplifier for comparing the reference voltage and the dividing voltage depending on the output signal of the edge trigger, and a switching means for charging an electric charge depending on the pumping voltage to the capacitor, depending on the output signal of the differential amplifier.
REFERENCES:
patent: 6233177 (2001-05-01), Shokouhi et al.
patent: 6249458 (2001-06-01), Shokouhi et al.
patent: 6285593 (2001-09-01), Wong
patent: 02003203491 (2003-07-01), None
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Nguyen Viet Q.
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